enclustra / en_cl_fixLinks
Fixed-point math library with VHDL, Python and MATLAB support
☆27Updated last month
Alternatives and similar repositories for en_cl_fix
Users that are interested in en_cl_fix are comparing it to the libraries listed below
Sorting:
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆34Updated 6 months ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆23Updated last year
- ☆33Updated 2 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Library of reusable VHDL components☆28Updated last year
- Repository containing the DSP gateware cores☆13Updated last week
- A simple DDR3 memory controller☆59Updated 2 years ago
- Network protocol libraries for VHDL test benches☆12Updated 4 months ago
- UART models for cocotb☆29Updated last week
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆50Updated last year
- Extensible FPGA control platform☆62Updated 2 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆75Updated last month
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆37Updated last year
- VHDL PCIe Transceiver☆30Updated 5 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆36Updated last week
- UART to AXI Stream interface written in VHDL☆16Updated 2 years ago
- An open-source HDL register code generator fast enough to run in real time.☆73Updated this week
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆24Updated 2 months ago
- Open FPGA Modules☆24Updated 11 months ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- Slides and lab instructions for the mastering MicroBlaze session☆36Updated 3 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- SDRAM controller for MIPSfpga+ system☆24Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- An open-source VHDL library for FPGA design.☆31Updated 3 years ago
- Interfacing VHDL and foreign languages with VUnit☆15Updated 5 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- Common SystemVerilog RTL modules for RgGen☆13Updated last week