enclustra / en_cl_fix
Fixed-point math library with VHDL, Python and MATLAB support
☆22Updated 2 months ago
Alternatives and similar repositories for en_cl_fix:
Users that are interested in en_cl_fix are comparing it to the libraries listed below
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 2 months ago
- Interfacing VHDL and foreign languages with VUnit☆14Updated 5 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated last year
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆23Updated 9 months ago
- An open-source HDL register code generator fast enough to run in real time.☆63Updated this week
- ☆33Updated 2 years ago
- Library of reusable VHDL components☆28Updated last year
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆23Updated 5 months ago
- Example of Test Driven Design with VUnit☆14Updated 3 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- UART models for cocotb☆28Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- submission repository for efabless mpw6 shuttle☆30Updated last year
- cryptography ip-cores in vhdl / verilog☆40Updated 4 years ago
- ☆41Updated last year
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- ☆13Updated 4 months ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- Slides and lab instructions for the mastering MicroBlaze session☆35Updated 2 years ago
- JESD204B core for Migen/MiSoC☆36Updated 4 years ago
- ☆21Updated 3 weeks ago
- SystemVerilog Linter based on pyslang☆30Updated 4 months ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 7 months ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆14Updated 2 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Updated last year
- File editor for the Xilinx AXI Traffic Generator IP☆16Updated 5 months ago
- An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…☆27Updated 3 months ago
- Open FPGA Modules☆23Updated 6 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- AXI Stream UART (verilog)☆11Updated 5 years ago