Alternatives and similar repositories for en_cl_fix

Users that are interested in en_cl_fix are comparing it to the libraries listed below

• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆39Updated 10 months ago
• suoto / fpga_cores
  ☆33Updated 2 years ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆26Updated last year
• lnls-dig / dsp-cores
  Repository containing the DSP gateware cores
  ☆14Updated last month
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆24Updated 5 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆53Updated 2 years ago
• geddy11 / netwiz
  Network protocol libraries for VHDL test benches
  ☆13Updated 7 months ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆42Updated 3 months ago
• noasic / noasic
  An open-source VHDL library for FPGA design.
  ☆32Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆25Updated 5 months ago
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆15Updated 5 years ago
• Cognoscan / BoostDSP
  VHDL Library for implementing common DSP functionality.
  ☆30Updated 7 years ago
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆32Updated 5 years ago
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆13Updated 7 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆41Updated 8 years ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆39Updated 5 years ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆36Updated 5 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆42Updated last year
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆41Updated 7 years ago
• fransschreuder / 8b10b_VHDL
  An 8b10b decoder and encoder in logic in VHDL
  ☆25Updated 4 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆17Updated 3 years ago
• VHDL / Interfaces
  Interface definitions for VHDL-2019.
  ☆34Updated 2 weeks ago
• lnls-dig / general-cores
  general-cores
  ☆21Updated 5 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆79Updated last week
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆32Updated 3 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆76Updated 5 months ago