enclustra / en_cl_fix
Fixed-point math library with VHDL, Python and MATLAB support
☆22Updated last month
Alternatives and similar repositories for en_cl_fix:
Users that are interested in en_cl_fix are comparing it to the libraries listed below
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated last month
- ☆33Updated last year
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆23Updated 9 months ago
- Library of reusable VHDL components☆28Updated last year
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆22Updated 4 months ago
- JESD204b modules in VHDL☆29Updated 5 years ago
- Slides and lab instructions for the mastering MicroBlaze session☆35Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated last year
- Example of Test Driven Design with VUnit☆14Updated 3 years ago
- UART to AXI Stream interface written in VHDL☆16Updated 2 years ago
- Open FPGA Modules☆23Updated 6 months ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- Interfacing VHDL and foreign languages with VUnit☆14Updated 5 years ago
- ☆13Updated 4 months ago
- An open-source HDL register code generator fast enough to run in real time.☆59Updated this week
- OSVVM Documentation☆33Updated 2 weeks ago
- IP Cores that can be used within Vivado☆25Updated 3 years ago
- UART models for cocotb☆27Updated 2 years ago
- This repository contains synthesizable examples which use the PoC-Library.☆37Updated 4 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Updated last year
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- Repository containing the DSP gateware cores☆12Updated 6 months ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- Extensible FPGA control platform☆59Updated last year
- ☆41Updated last year
- AXI Stream UART (verilog)☆11Updated 5 years ago