Alternatives and similar repositories for en_cl_fix:

Users that are interested in en_cl_fix are comparing it to the libraries listed below

• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated 3 weeks ago
• suoto / fpga_cores
  ☆33Updated last year
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• VUnit / tdd-intro
  Example of Test Driven Design with VUnit
  ☆14Updated 3 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆58Updated this week
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆34Updated 11 months ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated 2 years ago
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆23Updated 8 months ago
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆14Updated 5 years ago
• ATaylorCEngFIET / Mastering-MicroBlaze
  Slides and lab instructions for the mastering MicroBlaze session
  ☆35Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆53Updated 5 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• sbourdeauducq / serdes-tdc
  SERDES-based TDC core for Spartan-6
  ☆18Updated 12 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 8 years ago
• lnls-dig / dsp-cores
  Repository containing the DSP gateware cores
  ☆12Updated 5 months ago
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆27Updated 2 months ago
• wyvernSemi / mem_model
  High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
  ☆22Updated 4 months ago
• schang412 / cocotbext-spi
  ☆20Updated last week
• efard / DSPHDL
  ☆41Updated last year
• wallento / cocotbext-wishbone
  ☆13Updated 3 months ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆27Updated last year
• PyFPGA / HDLconv
  HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…
  ☆24Updated 2 weeks ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated last month
• paulscherrerinstitute / VivadoScripting
  Python Utilities to use Xilinx Vivado Tools from Python Scripts
  ☆17Updated 4 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆26Updated 2 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆23Updated 5 months ago
• tgingold-cern / cheby
  ☆12Updated 3 weeks ago