Fixed-point math library with VHDL, Python and MATLAB support
☆39Apr 13, 2026Updated 3 months ago
Alternatives and similar repositories for en_cl_fix
Users that are interested in en_cl_fix are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆29Jul 7, 2026Updated 3 weeks ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆41Feb 24, 2025Updated last year
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- ☆33Jul 15, 2026Updated last week
- An open-source HDL register code generator fast enough to run in real time.☆91Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆33Aug 20, 2022Updated 3 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆217Updated this week
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 4 months ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆43Sep 22, 2025Updated 10 months ago
- Open Logic FPGA Standard Library☆991Jul 8, 2026Updated 2 weeks ago
- An open-source VHDL library for FPGA design.☆32Jun 2, 2022Updated 4 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- Synthesizable FIR filters in VHDL☆15Jul 19, 2019Updated 7 years ago
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 12 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Nitro E1 FPGA core☆13Apr 30, 2024Updated 2 years ago
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆82Jun 21, 2026Updated last month
- ☆18Sep 16, 2020Updated 5 years ago
- ☆19Jul 20, 2026Updated last week
- VHDL dependency analyzer☆25Mar 10, 2020Updated 6 years ago
- ☆28Jul 7, 2026Updated 3 weeks ago
- Ref design combining the Zynq UltraScale+ MPSoC with the Hailo AI accelerator☆36Jul 7, 2026Updated 3 weeks ago
- VHDL code examples for a digital design course☆25Jan 29, 2020Updated 6 years ago
- cryptography ip-cores in vhdl / verilog☆42Feb 20, 2021Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A huge VHDL library for FPGA and digital ASIC development☆476Updated this week
- Library of reusable VHDL components☆28Mar 7, 2024Updated 2 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 3 years ago
- ☆21Mar 5, 2023Updated 3 years ago
- cocotb extension for nMigen☆17Feb 26, 2022Updated 4 years ago
- Resources for my first book☆23Jun 21, 2023Updated 3 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 5 months ago
- Source for the "FPGAs?! Now What?" Book☆66Jun 19, 2014Updated 12 years ago
- SystemVerilog RTL and UVM RAL model generators for RgGen☆17Jul 1, 2026Updated 3 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A simple 16bit system-on-chip (SoC) consisting of a CPU and GPU☆32Jun 3, 2025Updated last year
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆135Feb 11, 2021Updated 5 years ago
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆150Mar 29, 2026Updated 4 months ago
- LimeSDR XTRX gateware project.☆22Jan 20, 2026Updated 6 months ago
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- assorted library of utility cores for amaranth HDL☆105Sep 17, 2024Updated last year