Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our ow…
☆37Feb 23, 2025Updated last year
Alternatives and similar repositories for openXC7-TetriSaraj
Users that are interested in openXC7-TetriSaraj are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Digital systems are clocked. This project is about constructing a high-Q clock by simmering an ordinary quartz crystal in a heavy numeric…☆22Updated this week
- A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video …☆80Dec 30, 2025Updated 3 months ago
- Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…☆92Feb 26, 2026Updated last month
- A compact, configurable RISC-V core☆13Jul 31, 2025Updated 7 months ago
- Master-thesis-final☆19Oct 9, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek sec…☆1,321Mar 12, 2026Updated 2 weeks ago
- Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes. Now for the first time in opensource…☆61Feb 28, 2026Updated last month
- Simple extension boards for Olimex GateMate FPGA Board☆20Jun 30, 2025Updated 9 months ago
- Some assorted examples of nmigen designs☆19Nov 5, 2023Updated 2 years ago
- The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With sta…☆64Feb 24, 2026Updated last month
- An embeddable FPGA SoM designed for high-speed audio and USB applications.☆27Mar 9, 2026Updated 2 weeks ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆16Mar 3, 2026Updated 3 weeks ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆11Dec 14, 2022Updated 3 years ago
- Experimental Lattice ECP5-driven Data Center Security Communication Module☆20Jul 22, 2024Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Artix7 SOM☆19Sep 9, 2024Updated last year
- Fault Injection Automatic Test Equipment☆16Nov 22, 2021Updated 4 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆60Nov 14, 2025Updated 4 months ago
- assorted library of utility cores for amaranth HDL☆103Sep 17, 2024Updated last year
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- CRUVI Standard Specifications☆21May 6, 2024Updated last year
- "The Drop" ASIC 640x480 60Hz audio visual demo☆14Feb 11, 2026Updated last month
- CologneChip GateMate FPGA Module: GMM-7550☆29Jan 17, 2026Updated 2 months ago
- ☆12Jun 4, 2021Updated 4 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆38Jan 11, 2026Updated 2 months ago
- ☆24Jan 12, 2024Updated 2 years ago
- nMigen examples for the ULX3S board☆12May 5, 2022Updated 3 years ago
- Hardware Design/Visualization/Simulation/RTLGeneration Framework☆16Mar 12, 2026Updated 2 weeks ago
- Experiments with Marsohod3GW board with Gowin FPGA chip☆17May 8, 2025Updated 10 months ago
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆72Feb 12, 2026Updated last month
- Miscellaneous ULX3S examples (advanced)☆83Feb 7, 2026Updated last month
- ☆22Feb 3, 2026Updated last month
- basic example of litex on colorLight 5A-75B based on fpga_101/lab004☆38Jan 11, 2023Updated 3 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Fixed-point math library with VHDL, Python and MATLAB support☆38Oct 15, 2025Updated 5 months ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆36Mar 18, 2026Updated last week
- Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL☆112Jul 20, 2024Updated last year
- Another world port ESP32 TTGO VGA32 v1.4☆13Sep 23, 2024Updated last year
- Generate animated vector graphics for old-school 90's demos, like ST_NICCC☆18Jan 2, 2024Updated 2 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆27Jul 11, 2024Updated last year
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated last month