GSI-CS-CO / bel_projectsLinks
GSI Timing Gateware and Tools
☆14Updated this week
Alternatives and similar repositories for bel_projects
Users that are interested in bel_projects are comparing it to the libraries listed below
Sorting:
- A collection of Opal Kelly provided design resources☆17Updated 2 months ago
- Time to Digital Converter (TDC)☆36Updated 5 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- general-cores☆21Updated 5 months ago
- LMAC Core1 - Ethernet 1G/100M/10M☆19Updated 2 years ago
- VHDL functional blocks with their simulations and test sequences☆20Updated 2 weeks ago
- Verilog modules for software-defined radio.☆18Updated 13 years ago
- An open-source VHDL library for FPGA design.☆32Updated 3 years ago
- VHDL PCIe Transceiver☆32Updated 5 years ago
- UART to AXI Stream interface written in VHDL☆18Updated 3 years ago
- Repository containing the DSP gateware cores☆14Updated last month
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆12Updated 5 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆39Updated 10 months ago
- Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.☆20Updated 10 years ago
- Utilities for Avalon Memory Map☆11Updated last year
- 📊 Tools collection (NumPy + Matplotlib based) to do spectral analysis and calculate the key performance parameters of an ADC☆23Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆30Updated 4 years ago
- JESD204B core for Migen/MiSoC☆35Updated 4 years ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- ☆18Updated 5 years ago
- ☆20Updated 3 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Updated 7 years ago
- Open FPGA Modules☆24Updated last year
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆21Updated 11 months ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 months ago
- A flexible and scalable development platform for modern FPGA projects.☆39Updated last month
- Testbenches for HDL projects☆22Updated 3 weeks ago
- This is a C library to interface with the LiteX Firmware on Thunderscope over PCIe☆11Updated this week