wnew / hdl_library
A library of verilog and vhdl modules
☆15Updated 6 years ago
Alternatives and similar repositories for hdl_library:
Users that are interested in hdl_library are comparing it to the libraries listed below
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- Verilog RTL Design☆32Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆11Updated 3 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆28Updated 2 years ago
- Python Tool for UVM Testbench Generation☆52Updated 10 months ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 11 months ago
- WISHBONE Interconnect☆11Updated 7 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- ☆40Updated 3 years ago
- SERDES-based TDC core for Spartan-6☆18Updated 12 years ago
- APB UVC ported to Verilator☆11Updated last year
- ☆19Updated 5 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated last week
- To design test bench of the APB protocol☆17Updated 4 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆42Updated 10 months ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- Various utilities for working with FPGAs☆11Updated 9 years ago
- Asynchronous fifo in verilog☆33Updated 9 years ago
- This repo contain the PY-UVM Framework for different RISC-V Cores☆31Updated last year
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated 11 months ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- Reed Solomon Decoder (204,188)☆12Updated 10 years ago
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆20Updated 6 years ago
- Open FPGA Modules☆23Updated 5 months ago