wnew / hdl_library
A library of verilog and vhdl modules
☆14Updated 6 years ago
Alternatives and similar repositories for hdl_library:
Users that are interested in hdl_library are comparing it to the libraries listed below
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- WISHBONE Interconnect☆11Updated 7 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆16Updated 8 months ago
- Python Tool for UVM Testbench Generation☆50Updated 7 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- An example Python-based MDV testbench for apbi2c core☆30Updated 5 months ago
- UART models for cocotb☆24Updated last year
- Verilog RTL Design☆30Updated 3 years ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆19Updated 2 months ago
- APB UVC ported to Verilator☆11Updated last year
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆36Updated 4 years ago
- AXI Stream UART (verilog)☆11Updated 5 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆18Updated 5 months ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆28Updated 9 months ago
- Collection of IPs based on AMBA (AHB, APB, AXI) protocols☆19Updated 7 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- ☆20Updated 5 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆13Updated 10 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆26Updated 3 weeks ago
- AXI3 Bus Functional Models (Initiator & Target)☆27Updated 2 years ago
- SoC Based on ARM Cortex-M3☆25Updated this week
- This repo contain the PY-UVM Framework for different RISC-V Cores☆31Updated last year
- ☆23Updated 10 months ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆21Updated last month
- ☆40Updated 2 years ago
- Repository gathering basic modules for CDC purpose☆51Updated 5 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆41Updated 4 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆44Updated 8 years ago