embench / embench-iot
The main Embench repository
☆273Updated 7 months ago
Alternatives and similar repositories for embench-iot:
Users that are interested in embench-iot are comparing it to the libraries listed below
- ☆150Updated last year
- Working draft of the proposed RISC-V Bitmanipulation extension☆210Updated last year
- PLIC Specification☆141Updated 2 years ago
- Working Draft of the RISC-V Debug Specification Standard☆483Updated last month
- RISC-V Processor Trace Specification☆181Updated 2 weeks ago
- Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)☆266Updated this week
- RISC-V RV64GC emulator designed for RTL co-simulation☆224Updated 4 months ago
- RISC-V Debug Support for our PULP RISC-V Cores☆247Updated 5 months ago
- RISC-V Profiles and Platform Specification☆113Updated last year
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆208Updated last week
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆150Updated 2 years ago
- ☆170Updated last year
- ☆552Updated 2 weeks ago
- Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains☆149Updated this week
- RISC-V Torture Test☆189Updated 9 months ago
- RISC-V backports for binutils-gdb. Development is done upstream at the FSF.☆150Updated 2 years ago
- WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]☆141Updated last year
- Containing dozens of real-world and synthetic tests, CoreMark®-PRO (2015) is an industry-standard benchmark that measures the multi-proce…☆188Updated 8 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆229Updated 5 months ago
- FuseSoC-based SoC for VeeR EH1 and EL2☆312Updated 4 months ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆322Updated 3 years ago
- ☆131Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆155Updated 4 years ago
- ☆86Updated 2 years ago
- Instruction Set Generator initially contributed by Futurewei☆275Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆173Updated 8 months ago
- Fork of OpenOCD that has RISC-V support☆473Updated 2 weeks ago
- RISC-V CPU Core☆321Updated 10 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆223Updated last year
- Documentation for RISC-V Spike☆100Updated 6 years ago