Alternatives and similar repositories for riscv-formal

Users that are interested in riscv-formal are comparing it to the libraries listed below

• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated 10 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆158Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆194Updated 2 months ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 6 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆175Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated 2 weeks ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆114Updated 3 years ago
• chipsalliance / uvm-verilator
  ☆95Updated last year
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆174Updated 3 weeks ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆108Updated this week
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆207Updated this week
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆178Updated 6 months ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆77Updated this week
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆94Updated 2 weeks ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆159Updated 11 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated this week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆156Updated 4 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 6 months ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆76Updated 8 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆83Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆117Updated this week
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆78Updated last week
• pulp-platform / axi_riscv_atomics
  AXI Adapter(s) for RISC-V Atomic Operations
  ☆64Updated 3 weeks ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆159Updated last week
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆106Updated last week
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆137Updated 5 years ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆257Updated 2 weeks ago