Alternatives and similar repositories for riscv-formal

Users that are interested in riscv-formal are comparing it to the libraries listed below

• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆196Updated 11 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆163Updated last week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆151Updated 7 months ago
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆114Updated 3 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆175Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆196Updated 3 months ago
• chipsalliance / uvm-verilator
  ☆96Updated last year
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆211Updated this week
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆123Updated this week
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆105Updated last month
• ucsc-vama / essent
  high-performance RTL simulator
  ☆159Updated last year
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 7 months ago
• riscv-ovpsim / imperas-riscv-tests
  ☆179Updated last year
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆112Updated this week
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆178Updated 6 months ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆95Updated last month
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆165Updated this week
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆74Updated 6 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆82Updated this week
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆154Updated 2 weeks ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆109Updated 2 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆237Updated 7 months ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆73Updated last year
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆105Updated 9 years ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆77Updated 9 months ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆261Updated this week
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆67Updated last year