freecores / sgmii
SGMII
☆10Updated 10 years ago
Related projects ⓘ
Alternatives and complementary repositories for sgmii
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆13Updated last year
- Pipelined FFT/IFFT 64 points processor☆11Updated 10 years ago
- Reed Solomon Decoder (204,188)☆11Updated 10 years ago
- Quick'n'dirty FuseSoC+cocotb example☆17Updated 4 months ago
- A collection of SPI related cores☆15Updated 2 years ago
- SystemC to Verilog Synthesizable Subset Translator☆9Updated last year
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆13Updated 3 years ago
- Common SystemVerilog RTL modules for RgGen☆11Updated 5 months ago
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆11Updated 3 years ago
- MathLib DAC 2023 version☆12Updated last year
- Open FPGA Modules☆22Updated last month
- Generic AXI master stub☆19Updated 10 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆42Updated 11 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- ☆18Updated 10 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆12Updated 3 years ago
- Extended and external tests for Verilator testing☆15Updated this week
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- SystemVerilog Linter based on pyslang☆23Updated 7 months ago
- Ethernet interface modules for Cocotb☆56Updated last year
- IP-core package generator for AXI4/Avalon☆21Updated 5 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆22Updated 3 weeks ago
- ☆34Updated 9 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆23Updated last week
- Platform Level Interrupt Controller☆35Updated 6 months ago
- An Open Source Link Protocol and Controller☆25Updated 3 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆18Updated 3 months ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 6 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago