Alternatives and similar repositories for sca_pll

Users that are interested in sca_pll are comparing it to the libraries listed below

• Doulos / SystemC-Engine
  Explore the behavior SystemC kernel event-driven simulator (aka "the engine")
  ☆11Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆28Updated 3 years ago
• hichem / I2C
  SystemC Design of a Master/Slave I2C Bus
  ☆18Updated 10 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆40Updated 2 weeks ago
• matthiasschweikart / HDL-FSM-Editor
  A tool for modeling FSMs by VHDL or Verilog
  ☆11Updated last week
• jck / uhdl
  Utilities for MyHDL
  ☆19Updated last year
• sgherbst / anasymod
  A framework for FPGA emulation of mixed-signal systems
  ☆37Updated 4 years ago
• trusster / trusster
  Hardware Verification library for C++, SystemC and SystemVerilog
  ☆30Updated 12 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• TILhub / AMBA-3-AHB-Lite-Protocol
  This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol
  ☆13Updated 7 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆10Updated 5 years ago
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated 6 months ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated 2 weeks ago
• amiq-consulting / uvm_reg_to_ipxact
  ☆16Updated 6 years ago
• freecores / sc2v
  SystemC to Verilog Synthesizable Subset Translator
  ☆12Updated 2 years ago
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆22Updated 2 years ago
• Risto97 / systemc_uvm_verilator
  ☆13Updated 3 years ago
• accellera-official / systemc-common-practices
  SystemC Common Practices (SCP)
  ☆33Updated 11 months ago
• VP-Vibes / VPV-Peripherals
  Library of example SystemC/TLM peripherals for various SoCs based on the SCS library
  ☆14Updated 2 months ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆46Updated 10 years ago
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆19Updated last year
• go2uvm / go2uvm
  Main repo for Go2UVM source code, examples and apps
  ☆21Updated 2 years ago
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆25Updated 4 months ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 6 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆20Updated last week
• andreasWallner / spinalStuff
  ☆15Updated 11 months ago
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆13Updated 9 years ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆25Updated 4 years ago
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆24Updated 5 years ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 3 years ago