Alternatives and similar repositories for sca_pll

Users that are interested in sca_pll are comparing it to the libraries listed below

• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆29Updated 3 years ago
• Doulos / SystemC-Engine
  Explore the behavior SystemC kernel event-driven simulator (aka "the engine")
  ☆11Updated 2 years ago
• hichem / I2C
  SystemC Design of a Master/Slave I2C Bus
  ☆18Updated 10 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆10Updated 5 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆41Updated 2 months ago
• sgherbst / anasymod
  A framework for FPGA emulation of mixed-signal systems
  ☆39Updated 4 years ago
• andreasWallner / spinalStuff
  ☆15Updated last year
• jck / uhdl
  Utilities for MyHDL
  ☆19Updated 2 years ago
• trusster / trusster
  Hardware Verification library for C++, SystemC and SystemVerilog
  ☆30Updated 13 years ago
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated 9 months ago
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆13Updated 9 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆33Updated last month
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆45Updated 10 years ago
• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated 6 months ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 7 years ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 6 years ago
• bogdanvuk / sydpy
  System Design in Python (SyDPy) is a tool for design and verification of concurrent systems. The tool is offered as an alternative to Sys…
  ☆12Updated 9 years ago
• abs-tudelft / vhdeps
  VHDL dependency analyzer
  ☆24Updated 5 years ago
• Risto97 / systemc_uvm_verilator
  ☆13Updated 3 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated last month
• ganeshgore / spydrnet-physical
  This is a SpyDrNet Plugin for a physical design related transformations
  ☆16Updated 7 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• SpinalHDL / CocotbLib
  ☆18Updated 6 months ago
• freecores / sc2v
  SystemC to Verilog Synthesizable Subset Translator
  ☆12Updated 2 years ago
• SymbiFlow / sphinxcontrib-hdl-diagrams
  Sphinx Extension which generates various types of diagrams from Verilog code.
  ☆65Updated 2 years ago
• TILhub / AMBA-3-AHB-Lite-Protocol
  This Repo contains SystemC for testBench for AMBA® 3 AHB-Lite Protocol
  ☆13Updated 7 years ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆16Updated 9 years ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated 2 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year