Contains examples to start with Kactus2.
☆23Aug 5, 2024Updated last year
Alternatives and similar repositories for ipxactexamplelib
Users that are interested in ipxactexamplelib are comparing it to the libraries listed below
Sorting:
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆248Mar 13, 2026Updated last week
- ☆16May 10, 2019Updated 6 years ago
- An example OpenCAPI 3.0 FPGA reference design for accelerator endpoint development☆16Nov 7, 2022Updated 3 years ago
- IP-XACT XML binding library☆16Jun 23, 2016Updated 9 years ago
- IP-core package generator for AXI4/Avalon☆22Nov 25, 2018Updated 7 years ago
- Digital Circuit rendering engine☆39Jul 30, 2025Updated 7 months ago
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆65Jan 28, 2026Updated last month
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- Read-only mirror of https://chromium.googlesource.com/chromiumos/platform/depthcharge/. We don't handle pull requests.☆28Mar 12, 2026Updated last week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42May 24, 2020Updated 5 years ago
- UVM testbench for verifying the Pulpino SoC☆12Mar 23, 2020Updated 5 years ago
- Python bindings for coreir☆11Sep 13, 2023Updated 2 years ago
- EDA physical synthesis optimization kit☆64Nov 13, 2023Updated 2 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆11Sep 23, 2022Updated 3 years ago
- Signal analyzer CSV to IEEE 1364-2001 VCD file format converter.☆11Aug 13, 2021Updated 4 years ago
- This is a SpyDrNet Plugin for a physical design related transformations☆16Jun 13, 2025Updated 9 months ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆20Jan 5, 2023Updated 3 years ago
- Sample of project using UIO(User Space IO) Interrupt(ZYBO/Linux/PUMP_AXI4).☆13Nov 26, 2017Updated 8 years ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆31Mar 7, 2026Updated last week
- ☆43May 26, 2018Updated 7 years ago
- ☆25Feb 26, 2024Updated 2 years ago
- Official page for 18-847C (Spring '22): Data Center Computing☆15Apr 19, 2022Updated 3 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago
- Import and export IP-XACT XML register models☆37Nov 5, 2025Updated 4 months ago
- 🇯 JSON encoder and decoder in pure SystemVerilog☆14Jul 7, 2024Updated last year
- A c project for EDIF format parse.☆14May 10, 2016Updated 9 years ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆28Jan 21, 2026Updated last month
- Github Copilot-like LSP code completion server with local LLM powered by llama.cpp☆21Mar 11, 2024Updated 2 years ago
- Python-based IP-XACT parser and utilities☆143Jun 13, 2024Updated last year
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆76Apr 2, 2019Updated 6 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 6 years ago
- Wishbone to ARM AMBA 4 AXI☆16May 25, 2019Updated 6 years ago
- ☆10Oct 18, 2024Updated last year
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆30Oct 28, 2018Updated 7 years ago
- Web-based HDL diagramming tool☆83May 1, 2023Updated 2 years ago
- A library of verilog and vhdl modules☆15Nov 13, 2018Updated 7 years ago
- Multi-Dataflow Composer (MDC) design suite☆11Feb 13, 2026Updated last month
- D3.js and ELK based schematic visualizer☆115Feb 27, 2024Updated 2 years ago