Alternatives and similar repositories for hdl-make:

Users that are interested in hdl-make are comparing it to the libraries listed below

• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆53Updated last month
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆33Updated 4 months ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 3 months ago
• FPGA-Research / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆15Updated 5 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆56Updated last month
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆37Updated 10 months ago
• wohali / vcd_parsealyze
  A Value Change Dump (VCD) file parser and analyzer
  ☆19Updated 4 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆55Updated 5 months ago
• slaclab / axi-pcie-core
  ☆21Updated last week
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆74Updated this week
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆44Updated 2 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆40Updated 4 years ago
• drom / logidrom
  Digital Circuit rendering engine
  ☆38Updated last year
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆53Updated last year
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆43Updated 6 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated last week
• dbhi / vboard
  Virtual development board for HDL design
  ☆41Updated last year
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 6 months ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆21Updated 2 years ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• dalance / svls-vscode
  SystemVerilog language server client for Visual Studio Code
  ☆20Updated 2 years ago
• Cognoscan / AxiCores
  AXI4-Compatible Verilog Cores, along with some helper modules.
  ☆16Updated 5 years ago
• verilator / example-systemverilog
  ☆36Updated last year
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆44Updated 2 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆75Updated 4 years ago
• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆51Updated this week