HDLMake / hdl-makeLinks
Tool for generating multi-purpose makefiles for FPGA projects (clone of hdlmake from CERN)
☆16Updated 3 years ago
Alternatives and similar repositories for hdl-make
Users that are interested in hdl-make are comparing it to the libraries listed below
Sorting:
- ☆21Updated last week
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- hardware library for hwt (= ipcore repo)☆39Updated 2 weeks ago
- Small footprint and configurable Inter-Chip communication cores☆59Updated last month
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆70Updated 9 months ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆55Updated 3 weeks ago
- Platform Level Interrupt Controller☆41Updated last year
- Docker installation of Vivado tooling☆20Updated last week
- A SystemVerilog source file pickler.☆57Updated 8 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Re-coded Xilinx primitives for Verilator use☆49Updated this week
- Digital Circuit rendering engine☆39Updated last year
- CMake based hardware build system☆27Updated last week
- IEEE 754 single precision floating point library in systemverilog and vhdl☆30Updated 6 months ago
- SystemVerilog FSM generator☆32Updated last year
- An abstract language model of SystemVerilog (incl. Verilog) written in Python.☆9Updated last week
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated last year
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆47Updated 4 years ago
- ☆37Updated 2 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- VHDL PCIe Transceiver☆28Updated 4 years ago
- For contributions of Chisel IP to the chisel community.☆62Updated 7 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated 11 months ago
- ☆33Updated 2 years ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- IP-core package generator for AXI4/Avalon☆22Updated 6 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆36Updated 2 weeks ago
- ☆22Updated 8 years ago