Log file scanner used with EDA tools to classify errors and warnings
☆13Nov 14, 2022Updated 3 years ago
Alternatives and similar repositories for logscan
Users that are interested in logscan are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog wrapper over the Verilog Programming Interface (VPI)☆12Jun 3, 2025Updated last year
- Batch renames files from anime notation to TV series notation.☆14Mar 12, 2021Updated 5 years ago
- EDA Analytics Central☆16Dec 8, 2022Updated 3 years ago
- Bluespec H.264 Decoder☆12Jul 17, 2014Updated 12 years ago
- ☆13Aug 12, 2022Updated 4 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆10Oct 20, 2021Updated 4 years ago
- A simple dot file / graph generator for Verilog syntax trees.☆23Jul 16, 2016Updated 10 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Feb 21, 2020Updated 6 years ago
- A running collection of resources for people who want to get started in machine learning and data science☆18Dec 22, 2016Updated 9 years ago
- This repo is for the Linkedin Learning course: Training Neural Networks in C++☆14Oct 24, 2023Updated 2 years ago
- Simple template-based UVM code generator☆31Apr 15, 2026Updated 4 months ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 9 years ago
- Companion Material for the book: Building Embedded Systems - Programmable Hardware☆15Jun 6, 2016Updated 10 years ago
- VCD file viewer for Neovim☆15Feb 20, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Advanced Programming for Computer Design Problems☆17Aug 28, 2021Updated 5 years ago
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- Running Python code in SystemVerilog☆73May 8, 2026Updated 3 months ago
- A CSV file parser, written in SystemVerilog☆27Jul 13, 2016Updated 10 years ago
- A runtime DSL parser generator for python.☆18May 17, 2016Updated 10 years ago
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 9 months ago
- Embedded UVM (D Language port of IEEE UVM 1.0)☆34Nov 6, 2025Updated 9 months ago
- Kanban Board for Microsoft Outlook Tasks☆21Jan 12, 2024Updated 2 years ago
- A Value Change Dump (VCD) file parser and analyzer☆24Aug 27, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA wi…☆17Jan 4, 2020Updated 6 years ago
- Heterogeneous Programming☆19Apr 24, 2023Updated 3 years ago
- The Simulation Manager is a library for enabling reproducible scientific simulations.☆12May 1, 2023Updated 3 years ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆15May 7, 2022Updated 4 years ago
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- ☆11Apr 25, 2020Updated 6 years ago
- Digital Circuit rendering engine☆40Jul 9, 2026Updated last month
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 🚀 LLM inference optimization simulator, modeling compute-bound prefill and memory-bound decode phases.☆13Jul 12, 2025Updated last year
- Source code for LEF/DEF☆11Oct 16, 2018Updated 7 years ago
- Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster☆11Oct 14, 2021Updated 4 years ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆82Oct 22, 2024Updated last year
- A web crawler written in Python☆27Oct 2, 2020Updated 5 years ago
- Identify sources of winter air pollution in Bangkok☆23Feb 10, 2020Updated 6 years ago
- Support code for DVCon 2021 paper submission☆13Mar 1, 2021Updated 5 years ago