Alternatives and similar repositories for logscan

Users that are interested in logscan are comparing it to the libraries listed below

• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆26Updated 5 months ago
• tudortimi / vpi
  SystemVerilog wrapper over the Verilog Programming Interface (VPI)
  ☆13Updated 2 months ago
• tudortimi / reflection
  Reflection API for SystemVerilog
  ☆14Updated 2 months ago
• TUK-SCVP / SCVP.artifacts
  Artifacts for the SCVP lecture
  ☆10Updated 3 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆10Updated 5 years ago
• funningboy / pyvpi_example
  use pivpi to drive testbench event
  ☆21Updated 9 years ago
• fvutils / vte
  Verification Template Engine is a Jinja2-based template engine targeted at verification engineers
  ☆14Updated last year
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated 2 months ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆39Updated 2 weeks ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆53Updated last year
• Doulos / SystemC-Engine
  Explore the behavior SystemC kernel event-driven simulator (aka "the engine")
  ☆11Updated last year
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆25Updated 4 years ago
• Inkub / SV-assertions-IF-generator
  Generates a SystemVerilog assertion interface for a given SV RTL design
  ☆20Updated 4 months ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆35Updated last month
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆34Updated this week
• amiq-consulting / amiq_blog
  Code snippets from articles published on www.amiq.com/consulting/blog
  ☆36Updated last year
• ganeshgore / spydrnet-physical
  This is a SpyDrNet Plugin for a physical design related transformations
  ☆15Updated 2 months ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• bluwireless / blade
  Hardware Design, Exploration, and Code Generation for SoC Designers
  ☆11Updated 5 years ago
• mxg / svx
  SystemVerilog Extension Library -- a library of utilities for generic programming and increased productivity
  ☆30Updated last year
• agra-uni-bremen / crave
  Constrained random stimuli generation for C++ and SystemC
  ☆52Updated last year
• Risto97 / systemc_uvm_verilator
  ☆12Updated 2 years ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆16Updated 9 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆42Updated last month
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆45Updated 4 years ago
• amiq-consulting / amiq_ofc
  Open-Source Framework for Co-Emulation
  ☆12Updated 4 years ago
• edaa-org / pyEDAA.Reports
  Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.
  ☆14Updated this week
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆37Updated last month
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 3 years ago