agra-uni-bremen / crave
Constrained random stimuli generation for C++ and SystemC
☆50Updated last year
Alternatives and similar repositories for crave:
Users that are interested in crave are comparing it to the libraries listed below
- Python bindings for slang, a library for compiling SystemVerilog☆56Updated 3 months ago
- A header only C++11 library for functional coverage☆36Updated 2 years ago
- ☆20Updated this week
- ☆31Updated last year
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆60Updated last week
- Python packages providing a library for Verification Stimulus and Coverage☆120Updated this week
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆24Updated last month
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 3 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 6 months ago
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆55Updated 3 weeks ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆102Updated 3 weeks ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆44Updated 2 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆58Updated 3 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 7 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆50Updated 7 months ago
- use pivpi to drive testbench event☆21Updated 8 years ago
- ☆92Updated last year
- Running Python code in SystemVerilog☆68Updated 9 months ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…☆26Updated this week
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆92Updated 3 years ago
- A SystemVerilog source file pickler.☆56Updated 6 months ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- ☆49Updated 8 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆44Updated 4 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆33Updated 5 months ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆51Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆81Updated last year
- SystemVerilog Linter based on pyslang☆30Updated 3 months ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆77Updated 6 months ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago