agra-uni-bremen / craveLinks
Constrained random stimuli generation for C++ and SystemC
☆53Updated last year
Alternatives and similar repositories for crave
Users that are interested in crave are comparing it to the libraries listed below
Sorting:
- A header only C++11 library for functional coverage☆36Updated 3 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 4 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆127Updated 2 weeks ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆47Updated 4 years ago
- Code snippets from articles published on www.amiq.com/consulting/blog☆36Updated last year
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆26Updated 7 months ago
- ideas and eda software for vlsi design☆50Updated this week
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆71Updated this week
- use pivpi to drive testbench event☆21Updated 9 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆49Updated 2 months ago
- Implementation of post-process coverage, and batch waveform search☆16Updated 4 years ago
- Running Python code in SystemVerilog☆70Updated 4 months ago
- Import and export IP-XACT XML register models☆35Updated 3 weeks ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆39Updated 3 months ago
- Generate address space documentation HTML from compiled SystemRDL input☆57Updated 3 weeks ago
- A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.☆100Updated 3 years ago
- Python bindings for slang, a library for compiling SystemVerilog☆63Updated 8 months ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- ☆40Updated 10 years ago
- Generate UVM register model from compiled SystemRDL input☆59Updated 3 weeks ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated last year
- Translates IPXACT XML to synthesizable VHDL or SystemVerilog☆63Updated last month
- Open source RTL simulation acceleration on commodity hardware☆29Updated 2 years ago
- Test dashboard for verification features in Verilator☆27Updated last week
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆75Updated 2 months ago
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 4 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Updated last year
- ☆31Updated 2 years ago
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆79Updated 11 months ago
- ☆98Updated 2 years ago