Alternatives and similar repositories for AMBA-3-AHB-Lite-Protocol:

Users that are interested in AMBA-3-AHB-Lite-Protocol are comparing it to the libraries listed below

• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• Risto97 / VeriSC
  SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions
  ☆18Updated last month
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated last week
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆17Updated 6 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆33Updated 3 months ago
• trusster / trusster
  Hardware Verification library for C++, SystemC and SystemVerilog
  ☆29Updated 12 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆16Updated 8 months ago
• janweinstock / or1kmvp
  An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM
  ☆10Updated last year
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆20Updated 3 weeks ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆9Updated 4 years ago
• Risto97 / systemc_uvm_verilator
  ☆11Updated 2 years ago
• go2uvm / go2uvm
  Main repo for Go2UVM source code, examples and apps
  ☆20Updated last year
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆11Updated 8 years ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆11Updated this week
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆21Updated last month
• ezchi / uvm-systemc
  My local copy of UVM-SystemC
  ☆11Updated 8 months ago
• freecores / sc2v
  SystemC to Verilog Synthesizable Subset Translator
  ☆9Updated last year
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆34Updated 4 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆32Updated 10 years ago
• pulp-platform / axi_llc
  ☆21Updated last week
• embecosm / esp1-systemc-tlm
  Embecosm Software Package 1: Example SystemC loosely timed TLM 2.0 models
  ☆16Updated 11 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆17Updated 2 years ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆19Updated 2 years ago
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆14Updated 8 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆25Updated 3 months ago