Alternatives and similar repositories for AMBA-3-AHB-Lite-Protocol

Users that are interested in AMBA-3-AHB-Lite-Protocol are comparing it to the libraries listed below

• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆17Updated 6 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated this week
• Risto97 / VeriSC
  SystemC UVM verification environment with Constraint Randomized stimulus, Coverage, Assertions
  ☆19Updated 5 months ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆25Updated 2 weeks ago
• go2uvm / go2uvm
  Main repo for Go2UVM source code, examples and apps
  ☆20Updated 2 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆34Updated 7 months ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆20Updated 3 years ago
• Doulos / SystemC-Engine
  Explore the behavior SystemC kernel event-driven simulator (aka "the engine")
  ☆11Updated last year
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆17Updated last year
• ezchi / uvm-systemc
  My local copy of UVM-SystemC
  ☆12Updated last year
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆16Updated 8 years ago
• chiphackers / covered
  Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory…
  ☆31Updated 6 years ago
• Risto97 / systemc_uvm_verilator
  ☆12Updated 2 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆32Updated 3 months ago
• hdl / symbolator
  Generate symbols from HDL components/modules
  ☆21Updated 2 years ago
• iammituraj / FIFOs
  Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
  ☆17Updated 9 months ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆17Updated 2 years ago
• jkopanski / 802.15.4
  Medium Access Control layer of 802.15.4
  ☆12Updated 10 years ago
• rdiez / jtag_dpi
  JTAG DPI module for OpenRISC simulation with Verilator
  ☆17Updated 12 years ago
• trusster / trusster
  Hardware Verification library for C++, SystemC and SystemVerilog
  ☆30Updated 12 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆29Updated 10 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆38Updated 3 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆10Updated 5 years ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆18Updated 11 months ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆15Updated 3 months ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago