GHDL C extensions
☆12Feb 20, 2020Updated 6 years ago
Alternatives and similar repositories for ghdlex
Users that are interested in ghdlex are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A linux'ish build system for System on Chip designs, based on GHDL☆14Dec 14, 2024Updated last year
- A wrapper for GHDL to make it look like Mentor's ModelSim. Helpful for use with programs like Sigasi.☆11Jan 21, 2018Updated 8 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 3 years ago
- ☆20May 5, 2020Updated 6 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆56Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- VHDL String Formatting Library☆27Apr 27, 2024Updated 2 years ago
- Generate conversions to/from VHDL types and std_logic_vector. Generate python-based tests.☆12Jul 7, 2026Updated 3 months ago
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- VHDLproc is a VHDL preprocessor☆25May 12, 2022Updated 4 years ago
- Generate symbols from HDL components/modules☆23Feb 6, 2023Updated 3 years ago
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Sep 1, 2026Updated last month
- Trying to verify Verilog/VHDL designs with formal methods and tools☆44Mar 7, 2024Updated 2 years ago
- ☆17Apr 20, 2023Updated 3 years ago
- cryptography ip-cores in vhdl / verilog☆43Feb 20, 2021Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Unified Coverage Interoperability Standard (UCIS)☆15Updated this week
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆17May 23, 2020Updated 6 years ago
- A Sphinx domain providing VHDL language support.☆21Updated this week
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 6 years ago
- Retro computing on the Ulx3s ECP5 FPGA board☆26Mar 3, 2022Updated 4 years ago
- Connect to your VHDL simulation via JTAG! GDB <-TCP-> OpenOCD <-remote bitbang-> cosim_jtag <-VHPI or FLI-> VHDL simulator.☆15Dec 30, 2025Updated 9 months ago
- Network protocol libraries for VHDL test benches☆14Mar 9, 2026Updated 7 months ago
- Generator for VHDL regular expression matchers☆15Jan 11, 2021Updated 5 years ago
- JavaScript action for users to easily install tip/nightly GHDL assets in GitHub Actions workflows☆16Jan 12, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.☆18Sep 10, 2026Updated last month
- Dockerized FPGA toolchain experiments☆30Feb 10, 2024Updated 2 years ago
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆13Jan 15, 2017Updated 9 years ago
- Examples and design pattern for VHDL verification☆15Apr 10, 2016Updated 10 years ago
- Example of Test Driven Design with VUnit☆16Nov 22, 2021Updated 4 years ago
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- ☆33Jun 16, 2024Updated 2 years ago
- 🔍 Zoomable Waveform viewer for the Web☆43Nov 3, 2020Updated 5 years ago
- Virtual development board for HDL design☆44Mar 31, 2023Updated 3 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 4 years ago
- Repo to help explain the different options users have for packaging.☆19Jun 8, 2022Updated 4 years ago
- Interface definitions for VHDL-2019.☆36May 13, 2026Updated 5 months ago
- Cross EDA Abstraction and Automation☆45Updated this week
- FuseSoc Verification Automation☆22Jul 21, 2022Updated 4 years ago
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆70Feb 16, 2026Updated 8 months ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆71Jul 29, 2026Updated 3 months ago