hackfin / ghdlexLinks
GHDL C extensions
☆11Updated 5 years ago
Alternatives and similar repositories for ghdlex
Users that are interested in ghdlex are comparing it to the libraries listed below
Sorting:
- VHDL String Formatting Library☆27Updated last year
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Updated last year
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Updated 5 months ago
- VHDLproc is a VHDL preprocessor☆24Updated 3 years ago
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆62Updated 3 months ago
- VHDL related news.☆27Updated this week
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Updated 2 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Updated this week
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated last year
- VHDL dependency analyzer☆24Updated 5 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆51Updated 3 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.☆16Updated 9 months ago
- ☆20Updated 5 years ago
- A VHDL Core Library.☆18Updated 8 years ago
- 🔍 Zoomable Waveform viewer for the Web☆43Updated 5 years ago
- VHDL plugin for RgGen☆15Updated last month
- Open Source Verification Bundle for VHDL and System Verilog☆48Updated 2 years ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆32Updated 3 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- Interfacing VHDL and foreign languages with VUnit☆15Updated 5 years ago
- Streaming based VHDL parser.☆84Updated last year
- sample VCD files☆41Updated last month
- SpiceBind – spice inside HDL simulator☆56Updated 7 months ago
- Library of reusable VHDL components☆28Updated last year
- Proposal to define an XML-based logging format for outputs from EDA tools and logging libraries.☆14Updated 2 weeks ago
- Simple parser for extracting VHDL documentation☆74Updated last year
- Generate symbols from HDL components/modules☆22Updated 3 years ago
- FuseSoc Verification Automation☆22Updated 3 years ago
- Standard and Curated cores, tested and working.☆11Updated 3 years ago