Alternatives and similar repositories for vcd

Users that are interested in vcd are comparing it to the libraries listed below

• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆54Updated 2 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆84Updated 3 years ago
• wallento / wavedrompy
  WaveDrom compatible python command line
  ☆112Updated 2 years ago
• SanDisk-Open-Source / pyvcd
  Python package for writing Value Change Dump (VCD) files.
  ☆130Updated last year
• nanamake / vcd2json
  Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
  ☆40Updated last year
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆65Updated 2 months ago
• raczben / fliplot
  HTML & Js based VCD viewer
  ☆67Updated last week
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated 2 years ago
• sgherbst / svinst
  Determines the modules declared and instantiated in a SystemVerilog file
  ☆51Updated last year
• dpretet / svut
  SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
  ☆79Updated last year
• antmicro / cocotb-verilator-build
  ☆26Updated 2 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated 2 months ago
• gvekony / sv-1800-2012
  IEEE Std 1800™-2012: IEEE Standard for SystemVerilog -- Unified Hardware Design, Specification, and Verification Language syntax definiti…
  ☆33Updated last year
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆67Updated 5 months ago
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆47Updated 2 weeks ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆74Updated last month
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆33Updated last year
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆61Updated 3 weeks ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆71Updated 8 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆65Updated last year
• sgherbst / pysvinst
  Python library for parsing module definitions and instantiations from SystemVerilog files
  ☆26Updated 4 years ago
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆81Updated this week
• olofk / ipyxact
  Python-based IP-XACT parser and utilities
  ☆143Updated last year
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆26Updated 3 months ago
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆51Updated 7 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆77Updated 6 months ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated last month
• AndrewNolte / vscode-system-verilog
  SystemVerilog/Verilog support for vscode using Ctags
  ☆37Updated 4 months ago
• antmicro / verilator-verification
  Test dashboard for verification features in Verilator
  ☆29Updated this week