Alternatives and similar repositories for vcd:

Users that are interested in vcd are comparing it to the libraries listed below

• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆47Updated 8 months ago
• sgherbst / pysvinst
  Python library for parsing module definitions and instantiations from SystemVerilog files
  ☆22Updated 3 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆36Updated 3 months ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆52Updated last week
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆33Updated 3 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆48Updated 5 months ago
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆61Updated last year
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆55Updated last month
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆74Updated 9 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆67Updated 6 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆55Updated 2 months ago
• verilator / example-systemverilog
  ☆35Updated last year
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆35Updated 3 weeks ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆36Updated 9 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 7 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆37Updated 2 years ago
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 3 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 5 months ago
• fredrequin / verilator_xilinx
  Re-coded Xilinx primitives for Verilator use
  ☆43Updated 11 months ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆27Updated last month
• AndrewNolte / vscode-system-verilog
  SystemVerilog/Verilog support for vscode
  ☆23Updated this week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆112Updated 2 months ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆62Updated 2 months ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆51Updated last year
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆27Updated 9 months ago
• antmicro / verilator-verification-features-tests
  ☆17Updated this week
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆43Updated 4 years ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆74Updated this week