Alternatives and similar repositories for vcd:

Users that are interested in vcd are comparing it to the libraries listed below

• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆50Updated last month
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• nanamake / vcd2json
  Create WaveJSON from VCD file. WaveDrom can convert it to timing diagram.
  ☆35Updated 5 months ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆48Updated 4 months ago
• Nic30 / pyDigitalWaveTools
  Python library for operations with VCD and other digital wave files
  ☆47Updated 7 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• Nic30 / d3-wave
  D3.js based wave (signal) visualizer
  ☆61Updated 11 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 4 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆55Updated this week
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆55Updated 3 weeks ago
• raczben / fliplot
  HTML & Js based VCD viewer
  ☆59Updated 3 years ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 5 years ago
• sgherbst / pysvinst
  Python library for parsing module definitions and instantiations from SystemVerilog files
  ☆22Updated 3 years ago
• antmicro / verilator-verification-features-tests
  ☆17Updated this week
• SeanOBoyle / DoxygenFilterSystemVerilog
  ☆35Updated 9 years ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆79Updated 11 months ago
• wallento / wavedrompy
  WaveDrom compatible python command line
  ☆100Updated last year
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆35Updated last month
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆22Updated 3 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆37Updated last year
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆71Updated this week
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆29Updated this week
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆47Updated this week
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 6 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆68Updated last week
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆46Updated 8 months ago
• mciepluc / apbi2c_cocotb_example
  An example Python-based MDV testbench for apbi2c core
  ☆30Updated 5 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆40Updated this week
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆19Updated 4 years ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year