PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities
☆139Mar 3, 2026Updated this week
Alternatives and similar repositories for pcievhost
Users that are interested in pcievhost are comparing it to the libraries listed below
Sorting:
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆72Feb 12, 2026Updated 3 weeks ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- Open source ISS and logic RISC-V 32 bit project☆60Jan 20, 2026Updated last month
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- ice40 UltraPlus demos☆16Oct 4, 2019Updated 6 years ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆27Feb 2, 2026Updated last month
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Jul 15, 2024Updated last year
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102May 16, 2023Updated 2 years ago
- ☆21Sep 26, 2025Updated 5 months ago
- nMigen examples for the ULX3S board☆16Nov 30, 2020Updated 5 years ago
- PCI Express controller model☆73Oct 5, 2022Updated 3 years ago
- HDL tools layer for OpenEmbedded☆17Oct 20, 2024Updated last year
- ☆10Oct 23, 2016Updated 9 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 4 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆53Aug 7, 2023Updated 2 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- The binaries for SaxonSoc Linux and other configurations☆17Mar 23, 2023Updated 2 years ago
- PCIE 5.0 Graduation project (Verification Team)☆102Jan 27, 2024Updated 2 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆123Jul 22, 2021Updated 4 years ago
- ☆11May 8, 2022Updated 3 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- A library for PCIe Transaction Layer☆62Apr 27, 2022Updated 3 years ago
- PCIe analyzer experiments☆67May 21, 2020Updated 5 years ago
- Verilog PCI express components☆1,541Apr 26, 2024Updated last year
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated 3 weeks ago
- User-friendly explanation of Yosys options☆113Sep 25, 2021Updated 4 years ago
- ice40 USB Analyzer☆57Aug 8, 2020Updated 5 years ago
- A bit-serial CPU☆20Sep 29, 2019Updated 6 years ago
- crap-o-scope scope implementation for icestick☆20Jun 1, 2018Updated 7 years ago
- ☆18Aug 26, 2016Updated 9 years ago
- implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture☆108Jun 23, 2018Updated 7 years ago
- HW Design Collateral for Caliptra RoT IP☆130Feb 27, 2026Updated last week
- contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols☆63Feb 26, 2026Updated last week
- This is a software reference code to implement the FPGA remote debug feature. User will compile the reference code into a user space appl…☆14Feb 28, 2026Updated last week
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Nov 16, 2023Updated 2 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Jan 19, 2021Updated 5 years ago
- ☆13May 5, 2023Updated 2 years ago
- My pergola FPGA projects☆30Jun 23, 2021Updated 4 years ago
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated 9 months ago