Alternatives and similar repositories for pcievhost

Users that are interested in pcievhost are comparing it to the libraries listed below

• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆166Updated last month
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆105Updated 3 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆55Updated 2 years ago
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆54Updated this week
• chipsalliance / uvm-verilator
  ☆96Updated last year
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆54Updated 2 weeks ago
• shuckc / verilog-utils
  native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
  ☆44Updated 10 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆107Updated 3 years ago
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆37Updated 8 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆61Updated 3 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• oprecomp / DDR4_controller
  ☆59Updated 4 years ago
• lowRISC / ariane-ethernet
  open-source Ethenet media access controller for Ariane on Genesys-2
  ☆19Updated 5 years ago
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆55Updated 9 months ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆65Updated 7 months ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆57Updated 2 years ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆62Updated 3 weeks ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆104Updated 2 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆67Updated last year
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆62Updated 4 years ago
• alexforencich / cocotbext-i2c
  I2C models for cocotb
  ☆35Updated 3 months ago
• sach / System-Verilog-Packet-Library
  System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers
  ☆74Updated 6 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆136Updated this week
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆66Updated 6 months ago
• AngeloJacobo / DDR3-Notes
  My notes for DDR3 SDRAM controller
  ☆35Updated 2 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆82Updated 2 years ago