terpstra / opaLinks
Open Processor Architecture
☆26Updated 9 years ago
Alternatives and similar repositories for opa
Users that are interested in opa are comparing it to the libraries listed below
Sorting:
- OpenFPGA☆34Updated 7 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- Yosys Plugins☆22Updated 6 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- SoftCPU/SoC engine-V☆55Updated 8 months ago
- ☆63Updated 6 years ago
- RISC-V processor☆32Updated 3 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆70Updated 3 years ago
- ☆27Updated 9 months ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆91Updated 6 years ago
- Generic Logic Interfacing Project☆48Updated 5 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Updated last year
- PicoRV☆43Updated 5 years ago
- LatticeMico32 soft processor☆107Updated 11 years ago
- OpenRISC processor IP core based on Tomasulo algorithm☆33Updated 3 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆45Updated 3 years ago
- Yet Another RISC-V Implementation☆99Updated last year
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 5 years ago
- Next-Generation FPGA Place-and-Route☆10Updated 7 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Yet Another VHDL tool☆30Updated 8 years ago
- A RISC-V processor☆15Updated 7 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated this week