terpstra / opaLinks
Open Processor Architecture
☆26Updated 9 years ago
Alternatives and similar repositories for opa
Users that are interested in opa are comparing it to the libraries listed below
Sorting:
- OpenFPGA☆34Updated 7 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆75Updated 6 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 9 years ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- SoftCPU/SoC engine-V☆54Updated 5 months ago
- RISC-V processor☆31Updated 3 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- A Verilog Synthesis Regression Test☆37Updated last year
- Docker Development Environment for SpinalHDL☆20Updated last year
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated last year
- PicoRV☆44Updated 5 years ago
- Yosys Plugins☆21Updated 6 years ago
- A RISC-V processor☆15Updated 6 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 9 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Yet Another RISC-V Implementation☆96Updated 11 months ago
- ☆64Updated 6 years ago
- Benchmarks for Yosys development☆24Updated 5 years ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆29Updated 6 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks☆90Updated 6 years ago
- Xilinx Unisim Library in Verilog☆84Updated 5 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Python interface to FPGA interchange format☆41Updated 2 years ago
- Next-Generation FPGA Place-and-Route☆10Updated 7 years ago
- ☆27Updated 6 months ago