terpstra / opa
Open Processor Architecture
☆26Updated 8 years ago
Alternatives and similar repositories for opa:
Users that are interested in opa are comparing it to the libraries listed below
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- A Verilog Synthesis Regression Test☆35Updated 10 months ago
- Yosys Plugins☆21Updated 5 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 7 months ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated last year
- OpenFPGA☆33Updated 6 years ago
- RISC-V processor☆28Updated 2 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆72Updated 5 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 7 years ago
- SoftCPU/SoC engine-V☆54Updated last year
- A RISC-V processor☆13Updated 6 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- OpenRISC processor IP core based on Tomasulo algorithm☆31Updated 3 years ago
- ☆22Updated last year
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- Wishbone interconnect utilities☆38Updated last week
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆67Updated 2 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆35Updated 4 years ago
- ☆36Updated 2 years ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆26Updated 6 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago
- 👾 Design ∪ Hardware☆74Updated 3 months ago
- Parallel Array of Simple Cores. Multicore processor.☆94Updated 5 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- Small footprint and configurable Inter-Chip communication cores☆55Updated last month
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- A padring generator for ASICs☆25Updated last year
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago