Alternatives and similar repositories for cocotb-verilator-build

Users that are interested in cocotb-verilator-build are comparing it to the libraries listed below

• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆67Updated 8 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆64Updated 2 weeks ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆52Updated last year
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆30Updated 3 weeks ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• mciepluc / apbi2c_cocotb_example
  An example Python-based MDV testbench for apbi2c core
  ☆30Updated 10 months ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆43Updated 4 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆65Updated 7 months ago
• wallento / cocotbext-wishbone
  ☆13Updated 5 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆68Updated this week
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆53Updated last month
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 6 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated 3 months ago
• vsdip / vsdsram_sky130
  ☆41Updated 3 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆69Updated this week
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆59Updated 3 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆26Updated last year
• suoto / fpga_cores
  ☆32Updated 2 years ago
• schang412 / cocotbext-spi
  ☆21Updated last month
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆32Updated last week
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆54Updated this week
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆55Updated 2 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆34Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• sdnellen / open-register-design-tool
  Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
  ☆15Updated 5 months ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 5 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago