lambdaconcept / litesdcardLinks
☆25Updated 7 years ago
Alternatives and similar repositories for litesdcard
Users that are interested in litesdcard are comparing it to the libraries listed below
Sorting:
- ☆63Updated 5 years ago
- My pergola FPGA projects☆30Updated 4 years ago
- 妖刀夢渡☆63Updated 6 years ago
- ice40 USB Analyzer☆57Updated 5 years ago
- Low-cost ECP5 FPGA development board☆80Updated 5 years ago
- ☆44Updated 9 months ago
- USB Full-Speed core written in migen/LiteX☆43Updated 6 years ago
- A cheap iCE40 development board, designed on and for Raspberry Pi☆29Updated 6 years ago
- Tools and Examples for IcoBoard☆80Updated 4 years ago
- Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm☆34Updated 7 years ago
- ☆61Updated 2 years ago
- Experiments with Yosys cxxrtl backend☆50Updated 11 months ago
- Utilities for the ECP5 FPGA☆17Updated 4 years ago
- Example litex Risc-V SOC and some example code projects in multiple languages.☆70Updated 2 years ago
- USB Full-Speed core written in migen/LiteX☆12Updated 6 years ago
- Change part number or package in a Xilinx 7-series FPGA bitstream☆42Updated 5 years ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆90Updated last year
- Bootloader for Fomu☆104Updated 2 years ago
- MicroPython - legacy branch contain old experiments, and experimental for new work☆33Updated 4 years ago
- Utilities for working with a Wishbone bus in an embedded device☆47Updated 3 months ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆102Updated 2 years ago
- Cross compile FPGA tools☆21Updated 4 years ago
- A configurable USB 2.0 device core☆32Updated 5 years ago
- Tiny tips for Colorlight i5 FPGA board☆60Updated 4 years ago
- iCE40 floorplan viewer☆24Updated 7 years ago
- verilog core for ws2812 leds☆33Updated 4 years ago
- FPGA USB stack written in LiteX☆132Updated 3 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆39Updated 2 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 4 years ago
- Documenting the Anlogic FPGA bit-stream format.☆88Updated 2 years ago