fredrequin / verilator_gowin
Re-coded Gowin GW1N primitives for Verilator use
☆13Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for verilator_gowin
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆19Updated last month
- CologneChip GateMate FPGA Module: GMM-7550☆18Updated 9 months ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆40Updated last year
- Wishbone interconnect utilities☆37Updated 5 months ago
- RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K☆28Updated 7 months ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …