Re-coded Gowin GW1N primitives for Verilator use
☆21Aug 19, 2022Updated 3 years ago
Alternatives and similar repositories for verilator_gowin
Users that are interested in verilator_gowin are comparing it to the libraries listed below
Sorting:
- ☆28Dec 15, 2025Updated 2 months ago
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆35Feb 25, 2026Updated last week
- CologneChip GateMate FPGA Module: GMM-7550☆28Jan 17, 2026Updated last month
- UART cocotb module☆11Jun 30, 2021Updated 4 years ago
- Waveform Generator☆11Jul 18, 2022Updated 3 years ago
- Ruby Hardware Description Language☆15Mar 13, 2013Updated 12 years ago
- Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware☆13Aug 24, 2020Updated 5 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆59Nov 14, 2025Updated 3 months ago
- Simple extension boards for Olimex GateMate FPGA Board☆19Jun 30, 2025Updated 8 months ago
- Repository containing ULX3S blink LED binaries☆13May 16, 2022Updated 3 years ago
- ☆21Feb 3, 2026Updated last month
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38May 7, 2024Updated last year
- LunaPnR is a place and router for integrated circuits☆47Feb 11, 2026Updated 3 weeks ago
- Interactive code generators for Gowin FPGAs☆20Mar 16, 2023Updated 2 years ago
- ☆56Jul 22, 2022Updated 3 years ago
- Re-coded Xilinx primitives for Verilator use☆52Jun 24, 2025Updated 8 months ago
- an inverter drawn in magic with makefile to simulate☆27Jun 30, 2022Updated 3 years ago
- Repository with RP2040 simulation models.☆25Oct 11, 2025Updated 4 months ago
- VHDL String Formatting Library☆27Apr 27, 2024Updated last year
- A Just-In-Time Compiler for Verilog from VMware Research☆24Dec 14, 2020Updated 5 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆37Feb 23, 2025Updated last year
- ☆22Mar 5, 2022Updated 4 years ago
- Tutorials centred around Gowin FPGA parts for the /r/GowinFPGA subreddit☆62Mar 13, 2024Updated last year
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆66Jul 25, 2023Updated 2 years ago
- 🦀 No-nonsense hardware testing/simulation in Rust 🛠️ | Verilog, Spade, Veryl☆91Updated this week
- USB DFU bootloader gateware / firmware for FPGAs☆71Jan 30, 2026Updated last month
- Tests to evaluate the support of VHDL 2008 and VHDL 2019 features☆32Jan 30, 2025Updated last year
- Création d'étiquettes pour tableau électrique☆36Jul 23, 2025Updated 7 months ago
- A set of rules and recommendations for analog and digital circuit designers.☆31Nov 4, 2024Updated last year
- RV-Debugger-BL702 Project, an opensource debugger implement☆220Oct 31, 2024Updated last year
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Jul 15, 2024Updated last year
- My notes for DDR3 SDRAM controller☆43Feb 23, 2023Updated 3 years ago
- An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA☆91Oct 11, 2022Updated 3 years ago
- SpiceBind – spice inside HDL simulator☆56Jun 30, 2025Updated 8 months ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- Ease the Life of Verification Engineers by helping them to analyze and understand failing simulation faster☆11Oct 14, 2021Updated 4 years ago
- Raptor end-to-end FPGA Compiler and GUI☆96Dec 11, 2024Updated last year
- Verilog code to replace the Commodore SDMAC found in the A3000☆44Updated this week
- SystemVerilog frontend for Yosys☆203Feb 22, 2026Updated last week