Alternatives and similar repositories for zero-riscy

Users that are interested in zero-riscy are comparing it to the libraries listed below

• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆62Updated last year
• Ghonimo / Formal-Verification-With-VC-Formal--Tutorials-and-Examples
  This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…
  ☆31Updated last year
• ehao222 / ASIC-design-example-RISC-CPU
  Base on Synopsys platform using VCS,DC,ICC,PT.
  ☆12Updated 4 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆73Updated 7 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆41Updated last year
• kunalg123 / icc2_workshop_collaterals
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…
  ☆33Updated 5 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆57Updated last week
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆83Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆84Updated last week
• jmjos / ratatoskr
  Ratatoskr NoC Simulator
  ☆26Updated 4 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated 3 weeks ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 3 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆67Updated 6 months ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆40Updated 4 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆74Updated 5 years ago
• kuladeepsaireddy / OpenNoc
  ☆34Updated 6 years ago
• hyoukjun / microswitch-noc
  ☆27Updated 5 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆51Updated last year
• RPTU-EIS / upec-boom-verification-suite
  This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…
  ☆17Updated 2 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆42Updated 3 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆35Updated 4 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆75Updated 7 years ago
• yadav-sachin / Multilevel-Cache-Controller
  Cache Controller for a multi-level Cache memory using four-way set-associative mapping with write-back, no-write allocate and LRU policy.…
  ☆9Updated 4 years ago
• pulp-platform / axi-io-pmp
  Input / Output Physical Memory Protection Unit for RISC-V
  ☆12Updated last year
• bsg-idea / uw_openroad_free45
  UW reference flow for Free45PDK and The OpenROAD Project
  ☆11Updated 5 years ago
• IObundle / iob-versat
  Coarse Grained Reconfigurable Array
  ☆19Updated 4 months ago
• arhamhashmi01 / rv32i-pipeline-processor
  This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
  ☆14Updated 4 months ago
• vlsi-lab / len5
  LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.
  ☆16Updated last year
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆75Updated 10 years ago