zero-riscy CPU Core
☆19Jun 10, 2018Updated 8 years ago
Alternatives and similar repositories for zero-riscy
Users that are interested in zero-riscy are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 2 years ago
- rIC3 model checker for Hardware Model Checking Competition 2024(HWMCC'24) submission☆12Jul 4, 2025Updated 11 months ago
- Research project from UCI's AICPS lab: using GNNs to enable hardware security and prevent hardware trojans☆10Mar 31, 2021Updated 5 years ago
- ☆15Jun 18, 2023Updated 2 years ago
- Metal: Learning a Meta-Solver for Syntax-Guided Program Synthesis☆15Feb 18, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆13Jan 20, 2023Updated 3 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆13Nov 9, 2025Updated 7 months ago
- 开放验证平台NutShell Cache验证案例☆11Dec 2, 2025Updated 6 months ago
- Minimal OpenMSP430 hardware extensions for isolation and attestation☆24May 19, 2025Updated last year
- NLocalSAT; Boosting Local Search with Solution Prediction☆18Aug 4, 2023Updated 2 years ago
- ☆18Nov 19, 2023Updated 2 years ago
- ☆19Sep 12, 2022Updated 3 years ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 7 years ago
- "aura" my super-scalar O3 cpu core☆26May 25, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A RISC-V processor in system verilog☆12Jul 9, 2020Updated 5 years ago
- This repository contains all the information studied and created during the [Advanced Physical Design Using OpenLANE / SKY130](https://ww…☆17Jan 30, 2023Updated 3 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆11Jul 17, 2014Updated 11 years ago
- ☆42Apr 11, 2025Updated last year
- A 32-bit RISC-V processor for mriscv project☆61Jul 17, 2017Updated 8 years ago
- Command line loader program for the Au and Cu☆14Nov 28, 2023Updated 2 years ago
- Basic floating-point components for RISC-V processors☆12Aug 13, 2017Updated 8 years ago
- Mini RISC-V CPU☆11Dec 26, 2019Updated 6 years ago
- ☆11Jun 28, 2020Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Typhoon GPU on FPGA☆12Aug 22, 2019Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆37Oct 31, 2021Updated 4 years ago
- Wishbone SATA Controller☆26Oct 16, 2025Updated 7 months ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆16Nov 8, 2016Updated 9 years ago
- A generic parser and tool package for the BTOR2 format.☆48Sep 18, 2025Updated 8 months ago
- ☆21May 20, 2022Updated 4 years ago
- Implementation of a circular queue in hardware using verilog.☆17Mar 22, 2019Updated 7 years ago
- ☆13Dec 31, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Simple RiscV core for academic purpose.☆23Apr 29, 2020Updated 6 years ago
- IEEE 754 floating point unit in Verilog☆150May 20, 2016Updated 10 years ago
- RISC-V Static Binary Translator☆18Mar 6, 2019Updated 7 years ago
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆12Aug 22, 2021Updated 4 years ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago