asfhiolNick / NTU_PhysicalDesign_201902
張耀文老師的"奈米積體電路實體設計"作業(Physical Design)
☆8Updated last year
Alternatives and similar repositories for NTU_PhysicalDesign_201902:
Users that are interested in NTU_PhysicalDesign_201902 are comparing it to the libraries listed below
- Logic Synthesis and Verification: Programming Assignments☆12Updated 4 months ago
- Assignments of Physical Design for Nanometer ICs (Spring 2017, Prof. Yao-Wen Chang)☆39Updated 6 years ago
- Routing Visualization for Physical Design☆19Updated 6 years ago
- VLSI EDA Global Router☆72Updated 7 years ago
- ☆19Updated 7 months ago
- An open multiple patterning framework☆75Updated 11 months ago
- Open Source Detailed Placement engine☆38Updated 5 years ago
- 2019 NTHU CS6135 (CS613500) VLSI Physical Design Automation Course Projects (include Two-way Min-cut Partitioning, Fixed-outline Slicing …☆34Updated 3 weeks ago
- An open-source quantum automatic test generator.☆14Updated 7 months ago
- Library for VLSI CAD Design Useful parsers and solvers' api are implemented.☆157Updated 3 months ago
- Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization☆119Updated 4 months ago
- UCSD Detailed Router☆85Updated 4 years ago
- REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)☆55Updated 3 years ago
- Macro placement tool for OpenROAD flow☆23Updated 4 years ago
- Courseworks of CS6165 VLSI Physical Design Automation, NTHU.☆41Updated 4 years ago
- Power grid analysis☆19Updated 4 years ago
- CUGR, VLSI Global Routing Tool Developed by CUHK☆131Updated 2 years ago
- ☆77Updated 3 weeks ago
- C++ logic network library☆228Updated 6 months ago
- RePlAce global placement tool☆233Updated 4 years ago
- 🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit☆138Updated this week
- ☆10Updated 9 months ago
- Hardware Description Language on FPGA☆9Updated last year
- C++ implementation for Sequence Pair fixed-outline chip floorplanner☆11Updated 2 years ago
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆54Updated 4 years ago
- Pathfinder routing algorithm practice☆14Updated 7 years ago
- Steiner Shallow-Light Tree for VLSI Routing☆51Updated 9 months ago
- A parallel global router using the Galois framework☆27Updated last year
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆133Updated 2 years ago
- DATC RDF☆49Updated 4 years ago