FarisHijazi / LZ4-Decompressor-VerilogLinks
Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language
☆17Updated 6 years ago
Alternatives and similar repositories for LZ4-Decompressor-Verilog
Users that are interested in LZ4-Decompressor-Verilog are comparing it to the libraries listed below
Sorting:
- MMC (and derivative standards) host controller☆24Updated 5 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago
- IP Cores that can be used within Vivado☆26Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆46Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆28Updated 4 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated last month
- HW JPEG decoder wrapper with AXI-4 DMA☆36Updated 5 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆21Updated 8 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Updated 7 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Updated 9 years ago
- USB -> AXI Debug Bridge☆41Updated 4 years ago
- Xilinx JTAG Toolchain on Digilent Arty board☆18Updated 7 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Updated 6 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 5 years ago
- Imaging application using MIPI and DisplayPort to process image☆25Updated 5 years ago
- ☆30Updated 8 years ago
- Xilinx IP repository☆13Updated 7 years ago
- Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.☆13Updated 3 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆37Updated 7 years ago
- Generic AXI master stub☆19Updated 11 years ago
- Testbenches for HDL projects☆22Updated this week
- mirror of https://git.elphel.com/Elphel/eddr3☆41Updated 8 years ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- IP Catalog for Raptor.☆17Updated last year
- ☆35Updated 2 years ago
- WISHBONE Interconnect☆11Updated 8 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆16Updated last year
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 5 years ago