FarisHijazi / LZ4-Decompressor-Verilog
Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language
☆14Updated 6 years ago
Alternatives and similar repositories for LZ4-Decompressor-Verilog:
Users that are interested in LZ4-Decompressor-Verilog are comparing it to the libraries listed below
- SPI-Flash XIP Interface (Verilog)☆36Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆26Updated 3 years ago
- Groundhog - Serial ATA Host Bus Adapter☆22Updated 6 years ago
- MMC (and derivative standards) host controller☆23Updated 4 years ago
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆23Updated 6 months ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- Xilinx IP repository☆13Updated 6 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆12Updated 5 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆23Updated last month
- AXI DMA Check: A utility to measure DMA speeds in simulation☆14Updated 2 months ago
- QSPI for SoC☆22Updated 5 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆14Updated 2 years ago
- ☆14Updated 3 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- USB Full Speed PHY☆42Updated 4 years ago
- HDL and C source for WAVE Zynq Ultrascale+ SoC☆18Updated 3 years ago
- USB -> AXI Debug Bridge☆36Updated 3 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆31Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- Imaging application using MIPI and DisplayPort to process image☆23Updated 5 years ago
- ☆14Updated last year
- IP Cores that can be used within Vivado☆25Updated 3 years ago
- turbo 8051☆29Updated 7 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year