FarisHijazi / LZ4-Decompressor-VerilogLinks
Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language
☆16Updated 6 years ago
Alternatives and similar repositories for LZ4-Decompressor-Verilog
Users that are interested in LZ4-Decompressor-Verilog are comparing it to the libraries listed below
Sorting:
- MMC (and derivative standards) host controller☆24Updated 4 years ago
- Groundhog - Serial ATA Host Bus Adapter☆22Updated 7 years ago
- SPI-Flash XIP Interface (Verilog)☆39Updated 3 years ago
- Xilinx IP repository☆13Updated 7 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 3 years ago
- USB Full Speed PHY☆45Updated 5 years ago
- Testbenches for HDL projects☆19Updated last week
- Verilog IP Cores & Tests☆13Updated 7 years ago
- IP Cores that can be used within Vivado☆26Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Updated 7 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆34Updated 5 years ago
- ☆30Updated 8 years ago
- LMAC Core1 - Ethernet 1G/100M/10M☆17Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- ☆18Updated 3 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆20Updated 5 months ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆16Updated 5 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- Sata 2 Host Controller for FPGA implementation☆18Updated 7 years ago
- Generic AXI master stub☆19Updated 11 years ago
- Improved version of http://web.mit.edu/6.111/volume2/www/f2018/tools/sd_controller.v☆11Updated 3 years ago
- PNG encoder, implemented in VHDL☆23Updated last year
- 通过SPI协议实现FPGA multiboot在线升级功能☆11Updated 7 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆14Updated 6 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year