Alternatives and similar repositories for LZ4-Decompressor-Verilog

Users that are interested in LZ4-Decompressor-Verilog are comparing it to the libraries listed below

• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆48Updated 4 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆30Updated 4 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆24Updated 7 years ago
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆25Updated 5 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed3
  DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8
  ☆15Updated 2 months ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆35Updated 4 years ago
• BrianHGinc / Verilog-Floating-Point-Clock-Divider
  Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…
  ☆21Updated 11 months ago
• KutuSystems / XilinxIP
  Xilinx IP repository
  ☆13Updated 7 years ago
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆21Updated 8 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆27Updated 4 years ago
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆13Updated 7 years ago
• subutai-attic / pars
  ☆30Updated 8 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆36Updated 5 years ago
• analogdevicesinc / testbenches
  Testbenches for HDL projects
  ☆22Updated this week
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆83Updated 6 years ago
• ATaylorCEngFIET / Genesys_ZU_MIPI_PCAM
  Imaging application using MIPI and DisplayPort to process image
  ☆25Updated 5 years ago
• Elphel / x393_sata
  mirror of https://git.elphel.com/Elphel/x393_sata
  ☆33Updated 5 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆48Updated 5 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆42Updated 4 years ago
• hukenovs / adc_configurator
  ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
  ☆13Updated 7 years ago
• hellgate202 / crc_calc
  Simple and effective parallel CRC calculator written in synthesizable SystemVerilog
  ☆15Updated 6 years ago
• geraked / verilog-rle
  Verilog Implementation of Run Length Encoding for RGB Image Compression
  ☆27Updated 4 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆24Updated 11 years ago
• FDU-ME-ARC / NVMeCHA
  ☆20Updated 4 years ago
• ntpt7921 / Verilog_UDP_TCP
  Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.
  ☆13Updated 4 years ago
• FeldmeierMichael / MIPI_CSI_2
  ☆14Updated 2 years ago
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆41Updated 8 years ago
• semahawk / wishbone
  Trying to learn Wishbone by implementing few master/slave devices
  ☆13Updated 7 years ago
• mcrl / NVMe
  ☆36Updated 2 years ago