Alternatives and similar repositories for BIST_PUF_TRNG

Users that are interested in BIST_PUF_TRNG are comparing it to the libraries listed below

• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆33Updated 8 years ago
• Crimsonninja / senior_design_puf
  Repository to store all design and testbench files for Senior Design
  ☆19Updated 5 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆39Updated 5 years ago
• secworks / trng
  True Random Number Generator core implemented in Verilog.
  ☆75Updated 4 years ago
• p4r4xor / Montgomery1024
  Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation
  ☆10Updated 5 years ago
• scluconn / LPN-based_PUF
  FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.
  ☆15Updated 7 years ago
• ecelab-org / Split-Chip_authentication
  An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
  ☆17Updated 5 years ago
• shiva-t / Elliptical-Curve-Cryptography-FPGA
  Implementation of ECC on FPGA-Zynq7000 SoC
  ☆18Updated 6 years ago
• Gabalo / RO_PUF
  Ring Oscillator Physically Unclonable Funtion
  ☆24Updated 3 years ago
• fatestudio / RSA4096
  4096bit RSA project, with verilog code, python test code, etc
  ☆45Updated 5 years ago
• raymondrc / riscv-isa-extension-for-SM4
  RISC-V instruction set extensions for SM4 block cipher
  ☆20Updated 5 years ago
• ovpanait / zynq-aes
  AES hardware engine for Xilinx Zynq platform
  ☆31Updated 3 years ago
• lajanugen / Modular-Exponentiation
  Verilog Implementation of modular exponentiation using Montgomery multiplication
  ☆34Updated 10 years ago
• fabriziotappero / opencores-scraper
  few python scripts to clone all IP cores from opencores.org
  ☆24Updated last year
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆39Updated 4 years ago
• pansygrass / ecc
  Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…
  ☆46Updated 10 years ago
• ljgibbslf / SM2_core
  opensource crypto IP core
  ☆28Updated 4 years ago
• secworks / modexp
  Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
  ☆17Updated 4 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆66Updated 2 months ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆103Updated this week
• russdill / bch_verilog
  Verilog based BCH encoder/decoder
  ☆123Updated 2 years ago
• hyperpicc / ecc
  Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)
  ☆21Updated 7 years ago
• raymondrc / FPGA_SM4
  FPGA implementation of Chinese SM4 encryption algorithm.
  ☆55Updated 7 years ago
• mematrix / AES-FPGA
  AES加密解密算法的Verilog实现
  ☆67Updated 9 years ago
• heerambavi1998 / RSAonVerilog
  Implementation of RSA algorithm on FPGA using Verilog
  ☆28Updated 7 years ago
• Goshik92 / SHA256Hasher
  SHA-256 IP core for ZedBoard (Zynq SoC)
  ☆30Updated 7 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated 6 months ago
• ATaylorCEngFIET / introduction_to_vivado
  ☆20Updated 2 years ago
• ljhsiun2 / EllipticCurves_SystemVerilog
  Elgamal's over Elliptic Curves
  ☆19Updated 6 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago