Alternatives and similar repositories for AES_MATLAB

Users that are interested in AES_MATLAB are comparing it to the libraries listed below

• edstott / EE2Project
  EEE2/EIE2 Group Project
  ☆16Updated 3 months ago
• muneeb-mbytes / apb_avip
  ABP Accelerated VIP
  ☆22Updated 2 years ago
• trivedidvijen / SPI-to-I2C-Protocol-Conversion-Using-Verilog
  SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.
  ☆11Updated 4 years ago
• Grootzz / AD9361_TX_1MHz_Baseband_800Hz_IF
  A project demonstrate how to config ad9361 to TX mode
  ☆11Updated 6 years ago
• Aquaticfuller / OpenExSys_NoC
  OpenExSys_NoC a mesh-based network on chip IP.
  ☆16Updated last year
• chinkwo / FPGA-multiboot
  通过SPI协议实现FPGA multiboot在线升级功能
  ☆11Updated 7 years ago
• dylanmsu / BT656_to_AXI4S
  VHDL sources for a BT.656 to axi4-stream converter
  ☆11Updated 2 years ago
• donlon / axi-dma-controller
  Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. Work in Progress.
  ☆13Updated 11 months ago
• falwat / code_repo
  My code repositry for common use.
  ☆23Updated 3 years ago
• sfahmy / verilogtools
  Python tools for processing Verilog files
  ☆10Updated 13 years ago
• DOUDIU / AXIS-AXI4-AXIS
  This project is designed to delay the output of the video stream in AXI-STREAM format.
  ☆12Updated last year
• Shra1-25 / Deep-Learning-implementaion-on-FPGA-using-MATLAB
  This repository contains MATLAB code which can be used to generate simulink model and HDL code for implementation on FPGA. Since HDL code…
  ☆13Updated 5 years ago
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆15Updated 2 years ago
• hellgate202 / crc_calc
  Simple and effective parallel CRC calculator written in synthesizable SystemVerilog
  ☆14Updated 6 years ago
• haifengch / axi_interconnect
  ☆23Updated 2 months ago
• freecores / axi_master
  Generic AXI master stub
  ☆19Updated 11 years ago
• arpitp / ssd-controller
  Open Source SSD Controller. NVMe and Lightstor variants
  ☆16Updated 11 years ago
• guoyijiang / VerilogModule-IIC_Master
  this repository is a project about iic master, created by gyj in second half of 2017
  ☆18Updated 7 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed3
  DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8
  ☆15Updated 3 years ago
• Architech-Silica / Zynq-Configuration-Controller
  A configuration controller solution allowing a Zynq device to configure downstream FPGAs
  ☆14Updated 9 years ago
• crboth / AWGN_Generator
  FPGA Additive White Gaussian Noise Generator Using the Box Mueller Method
  ☆10Updated 8 years ago
• KutuSystems / XilinxIP
  Xilinx IP repository
  ☆13Updated 7 years ago
• semahawk / wishbone
  Trying to learn Wishbone by implementing few master/slave devices
  ☆12Updated 6 years ago
• fpgasystems / groundhog
  Groundhog - Serial ATA Host Bus Adapter
  ☆24Updated 7 years ago
• ZipCPU / axidmacheck
  AXI DMA Check: A utility to measure DMA speeds in simulation
  ☆15Updated 8 months ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆17Updated 11 years ago
• XBQ314 / A-Number-Theoretic-Transform-Accelerator-with-Two-Parallel-Simplified-Butterfly-Units
  Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现，基为2，有两个并行的蝶形单元
  ☆18Updated 3 years ago
• lnls-dig / dsp-cores
  Repository containing the DSP gateware cores
  ☆13Updated 2 weeks ago
• aignacio / ahb_lite_bus
  AHB Bus lite v3.0
  ☆16Updated 6 years ago
• zslwyuan / Zynq_HLS_DDR_Dataflow_kernel_2mm
  This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…
  ☆21Updated 6 years ago