dbossnirvana / AES_MATLABLinks
AES implementation in MATLAB
☆12Updated 9 years ago
Alternatives and similar repositories for AES_MATLAB
Users that are interested in AES_MATLAB are comparing it to the libraries listed below
Sorting:
- Verilog Implementation of the Number Theoretic Transform (NTT) and its inverse operation (INTT) utilizing modulo arithmetic for lattice-b…☆15Updated 2 months ago
- EEE2/EIE2 Group Project☆16Updated 7 months ago
- ABP Accelerated VIP☆22Updated 3 years ago
- A project demonstrate how to config ad9361 to TX mode☆11Updated 7 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆12Updated 4 years ago
- My code repositry for common use.☆23Updated 4 years ago
- FPGA Additive White Gaussian Noise Generator Using the Box Mueller Method☆11Updated 9 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Updated last year
- 通过SPI协议实现FPGA multiboot在线升级功能☆12Updated 7 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Updated last year
- OpenExSys_NoC a mesh-based network on chip IP.☆20Updated 2 years ago
- VHDL sources for a BT.656 to axi4-stream converter☆11Updated 2 years ago
- User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)☆11Updated 7 years ago
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现,基为2,有两个并行的蝶形单元☆19Updated 3 years ago
- This repository contains MATLAB code which can be used to generate simulink model and HDL code for implementation on FPGA. Since HDL code…☆13Updated 5 years ago
- Simple demo showing how to use the ping pong FIFO☆16Updated 9 years ago
- A configuration controller solution allowing a Zynq device to configure downstream FPGAs☆14Updated 10 years ago
- Utilities for Avalon Memory Map☆11Updated last year
- Design of High-Level Synthesis of Xilinx FFT IP core via FFT library☆13Updated 2 years ago
- A collection of Opal Kelly provided design resources☆17Updated 3 months ago
- Python tools for processing Verilog files☆10Updated 14 years ago
- this repository is a project about iic master, created by gyj in second half of 2017☆18Updated 7 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 2 months ago
- IP Catalog for Raptor.☆17Updated last year
- Verilog modules for software-defined radio.☆18Updated 13 years ago
- Xilinx IP repository☆13Updated 7 years ago
- ☆13Updated 2 weeks ago
- Generic AXI master stub☆19Updated 11 years ago
- Example design for the Ethernet FMC using an FPGA based hardware packet generator/checker to demonstrate maximum throughput☆12Updated last year
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆14Updated 7 years ago