vignesh-raghavan / AES128
Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.
☆14Updated 7 years ago
Alternatives and similar repositories for AES128:
Users that are interested in AES128 are comparing it to the libraries listed below
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆54Updated 2 years ago
- Architectural design of data router in verilog☆28Updated 5 years ago
- APB to I2C☆39Updated 10 years ago
- PCIE 5.0 Graduation project (Verification Team)☆61Updated last year
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆41Updated 4 years ago
- ☆39Updated 3 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆25Updated 4 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆116Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆26Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆38Updated 4 years ago
- AXI总线连接器☆94Updated 4 years ago
- AXI Interconnect☆47Updated 3 years ago
- SystemVerilog VIP for AMBA APB protocol☆71Updated 3 years ago
- AHB DMA 32 / 64 bits☆52Updated 10 years ago
- ☆16Updated 2 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆81Updated last year
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆57Updated last year
- Verification IP for APB protocol☆57Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆30Updated 2 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆145Updated 4 years ago
- UVM examples and projects☆125Updated 6 years ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- UVM Testbench For SystemVerilog Combinator Implementation☆53Updated 8 years ago
- UART design in SV and verification using UVM and SV☆40Updated 5 years ago
- ☆35Updated 9 years ago