siamumar / tinyAESLinks
☆21Updated 8 years ago
Alternatives and similar repositories for tinyAES
Users that are interested in tinyAES are comparing it to the libraries listed below
Sorting:
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆24Updated last year
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Updated 9 years ago
- The PE for the second generation CGRA (garnet).☆18Updated 9 months ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆67Updated 3 years ago
- pulp_soc is the core building component of PULP based SoCs☆82Updated 10 months ago
- A fork of Yosys that integrates the CellIFT pass☆13Updated 6 months ago
- SCARV: a side-channel hardened RISC-V platform☆22Updated 4 years ago
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 4 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Hardware Formal Verification☆17Updated 5 years ago
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores☆14Updated 2 weeks ago
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- ☆14Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 4 years ago
- ☆10Updated 4 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆39Updated 5 months ago
- ☆82Updated last year
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆128Updated 3 years ago
- An LLVM based mini-C to Verilog High-level Synthesis tool☆39Updated 10 months ago
- CNN accelerator☆29Updated 8 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆23Updated 2 weeks ago
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Updated 5 years ago
- Wallace and Dadda tree multiplier generator in vhdl and verilog☆12Updated last year
- Determines the modules declared and instantiated in a SystemVerilog file☆50Updated last year
- C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)☆53Updated 5 years ago