Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrated Circuits.
☆55Apr 29, 2015Updated 11 years ago
Alternatives and similar repositories for ecc
Users that are interested in ecc are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆22Oct 31, 2017Updated 9 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆31Sep 24, 2018Updated 8 years ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆21Jul 12, 2019Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- Novel GUI Based UVM Testbench Template Builder☆156Apr 14, 2021Updated 5 years ago
- Implements a simple UVM based testbench for a simple memory DUT.☆12Oct 26, 2019Updated 7 years ago
- MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.☆12Dec 27, 2022Updated 3 years ago
- Tensor computing core☆15Jul 8, 2026Updated 3 months ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 5 years ago
- Hamming ECC Encoder and Decoder to protect memories☆37Jan 28, 2025Updated last year
- syn script for DC Compiler☆15May 15, 2022Updated 4 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆37Apr 15, 2020Updated 6 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).☆32Jun 13, 2015Updated 11 years ago
- axi video dma ip in verilog☆11Aug 22, 2020Updated 6 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- CDC example code for CSDN blog☆14Oct 18, 2021Updated 5 years ago
- Dilithium is a digital signature scheme that is strongly secure under chosen message attacks based on the hardness of lattice problems ov…☆17Jul 28, 2023Updated 3 years ago
- CLI tool for RTL design space exploration on top of Vivado☆15Jun 5, 2023Updated 3 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆56Aug 14, 2024Updated 2 years ago
- ☆22Oct 12, 2026Updated 2 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- MMC (and derivative standards) host controller☆26Sep 14, 2020Updated 6 years ago
- A Flyweight MBIST Block - FPGA synthesizable, Multi-algorithm integrated☆19Jan 27, 2019Updated 7 years ago
- Using Nim to interface with SystemVerilog test benches via DPI-C☆32May 15, 2025Updated last year
- generate UVM testbench using python☆28Mar 24, 2018Updated 8 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Jun 1, 2023Updated 3 years ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆84Apr 28, 2023Updated 3 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆150May 14, 2021Updated 5 years ago
- ☆10Sep 7, 2023Updated 3 years ago
- Open-Channel Open-Way Flash Controller☆26Sep 10, 2021Updated 5 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Wishbone SATA Controller☆28Sep 17, 2026Updated last month
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 3 years ago
- ☆19Aug 25, 2017Updated 9 years ago
- ☆29Mar 1, 2025Updated last year
- Fast convolution algorithms with Python types☆10Nov 20, 2016Updated 9 years ago
- 简单的未优化的SRT除法器☆13Jun 16, 2024Updated 2 years ago
- Implementation of TFHE with Julia☆11Mar 25, 2020Updated 6 years ago