pansygrass / eccLinks
Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrated Circuits.
☆51Updated 10 years ago
Alternatives and similar repositories for ecc
Users that are interested in ecc are comparing it to the libraries listed below
Sorting:
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆84Updated 7 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆99Updated 5 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆73Updated last year
- Basic floating-point components for RISC-V processors☆67Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆41Updated 6 years ago
- ☆70Updated 4 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- AMBA bus generator including AXI, AHB, and APB☆117Updated 4 years ago
- DMA Hardware Description with Verilog☆18Updated 6 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆97Updated 6 years ago
- round robin arbiter☆77Updated 11 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- ☆66Updated 3 years ago
- SystemVerilog modules and classes commonly used for verification☆54Updated last month
- An AXI4 crossbar implementation in SystemVerilog☆199Updated 4 months ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆60Updated 3 weeks ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆87Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- This is the repository for the IEEE version of the book☆77Updated 5 years ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 3 weeks ago
- ☆99Updated 4 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated 3 weeks ago
- An Open-Source Design and Verification Environment for RISC-V☆86Updated 4 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆185Updated last year
- Verilog Content Addressable Memory Module☆113Updated 3 years ago
- SoC Based on ARM Cortex-M3☆34Updated 7 months ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12Updated 4 years ago