This project contains synthesized verilog codes for Encryption/Decryption of secure IP stream using Advanced Encryption Standard (AES) algorithm and implemented through Field Programmable Gate Array (FPGA). This is a very optimized code for handling IP packets and encrypt/decrypt the data part using a 128-bit block cipher. It uses a pipeline an…
☆17May 2, 2013Updated 13 years ago
Alternatives and similar repositories for IP_Stream_Encryption_using_AES_and_FPGA
Users that are interested in IP_Stream_Encryption_using_AES_and_FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 6 years ago
- Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.☆18Dec 16, 2017Updated 8 years ago
- C++ and Verilog to implement AES128☆24Apr 30, 2018Updated 8 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Apr 15, 2021Updated 5 years ago
- AES hardware engine for Xilinx Zynq platform☆32Aug 22, 2021Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- ☆27Feb 27, 2021Updated 5 years ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆15Dec 23, 2022Updated 3 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆35Dec 10, 2021Updated 4 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 7 years ago
- AES implementation in MATLAB☆12Nov 15, 2016Updated 9 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆11Aug 15, 2020Updated 5 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- Implementation of the CMAC keyed hash function using AES as block cipher.☆16Apr 2, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- AES☆15Oct 4, 2022Updated 3 years ago
- Zedboard projects☆11May 15, 2016Updated 10 years ago
- Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…☆451Dec 29, 2025Updated 6 months ago
- Speccy - The ChromeOS Amateur Radio Spectrum Analyzer☆14Mar 22, 2017Updated 9 years ago
- IEEE Executive project for the year 2021-2022☆11Nov 22, 2022Updated 3 years ago
- ☆47Feb 22, 2025Updated last year
- ☆15May 8, 2018Updated 8 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆14Jul 28, 2021Updated 4 years ago
- A repository for exploring LLM-assisted code conversion to TL-Verilog.☆15Apr 25, 2026Updated 2 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Verilog Language Extension for Visual Studio☆20Updated this week
- Publishes system data (bat. voltages, PV watts, etc) on the D-Bus. Gets this data from other D-Bus services.☆17Jun 26, 2026Updated last week
- ☆14May 11, 2022Updated 4 years ago
- An accurate Electro Cardio Graph system, with peak detection and counting mechanism programmed in Verilog.☆15Jan 6, 2019Updated 7 years ago
- 2020: Teensy 4.x as Audio USB to PCM5102 and ES9023 Audio DACs, with a USB Volume Control with an SSD1306 OLED peak meter. It requires c…☆12May 19, 2022Updated 4 years ago
- LZW Compressoion algorithm in verilog☆17Dec 19, 2013Updated 12 years ago
- AES-128 hardware implementation☆33May 4, 2020Updated 6 years ago
- Contenido práctico de la asignatura Señales y Sistemas de la carrera Ingeniería de Sonido, en la Universidad Nacional de Tres de Febrero.☆10Jun 18, 2026Updated 2 weeks ago
- Verilog Code for I2C Protocol☆19Nov 12, 2020Updated 5 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Radio Gyms is an open-source bundle of AI environments for radio communications.☆13May 10, 2022Updated 4 years ago
- RP-Sim is an environment for simulate the propagation of wireless communication.☆15May 13, 2021Updated 5 years ago
- GPSProbe allows you to record GPS, MAC address, signal strength etc. of wifi enabled devices nearby.☆19Oct 19, 2024Updated last year
- ☆18Jun 17, 2017Updated 9 years ago
- Verilog library for implementing neural networks.☆27Aug 19, 2014Updated 11 years ago
- The simple, stupid and slow HNCP daemon☆19Jul 31, 2023Updated 2 years ago
- Template Engine Benchmark Test☆16May 12, 2014Updated 12 years ago