This project contains synthesized verilog codes for Encryption/Decryption of secure IP stream using Advanced Encryption Standard (AES) algorithm and implemented through Field Programmable Gate Array (FPGA). This is a very optimized code for handling IP packets and encrypt/decrypt the data part using a 128-bit block cipher. It uses a pipeline an…
☆17May 2, 2013Updated 13 years ago
Alternatives and similar repositories for IP_Stream_Encryption_using_AES_and_FPGA
Users that are interested in IP_Stream_Encryption_using_AES_and_FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.☆18Dec 16, 2017Updated 8 years ago
- AES-based-on-FPGA developed by verilog.☆23Apr 23, 2020Updated 6 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Apr 15, 2021Updated 5 years ago
- AES hardware engine for Xilinx Zynq platform☆32Aug 22, 2021Updated 4 years ago
- The community version of HLS_BLSTM (A BLSTM FPGA accelerator of an OCR appilcation, using CAPI/SNAP))☆11Sep 27, 2019Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Advanced encryption standard implementation in verilog.☆31Oct 2, 2022Updated 3 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆35Dec 10, 2021Updated 4 years ago
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆17Jan 27, 2018Updated 8 years ago
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…☆17Mar 22, 2017Updated 9 years ago
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆24Jun 27, 2023Updated 2 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- Implementation of the CMAC keyed hash function using AES as block cipher.☆16Apr 2, 2025Updated last year
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- AES-128 Encryption☆11Jul 17, 2014Updated 11 years ago
- Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…☆442Dec 29, 2025Updated 4 months ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- Speccy - The ChromeOS Amateur Radio Spectrum Analyzer☆14Mar 22, 2017Updated 9 years ago
- ☆15May 8, 2018Updated 8 years ago
- A repository for exploring LLM-assisted code conversion to TL-Verilog.☆15Apr 25, 2026Updated last month
- Verilog Language Extension for Visual Studio☆20Jan 14, 2026Updated 4 months ago
- FPGA/AES/LeNet/VGG16☆108Sep 9, 2018Updated 7 years ago
- The PCI Utilities☆25Jun 21, 2024Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆62Mar 15, 2024Updated 2 years ago
- An accurate Electro Cardio Graph system, with peak detection and counting mechanism programmed in Verilog.☆15Jan 6, 2019Updated 7 years ago
- 16QAM modulation and demodulation by Verilog☆21Jan 4, 2021Updated 5 years ago
- AES-128 hardware implementation☆33May 4, 2020Updated 6 years ago
- Bitfile Interpretation Library for Xilinx Virtex FPGAs☆29Aug 9, 2012Updated 13 years ago
- ☆14May 11, 2022Updated 4 years ago
- ☆22Apr 4, 2024Updated 2 years ago
- Contenido práctico de la asignatura Señales y Sistemas de la carrera Ingeniería de Sonido, en la Universidad Nacional de Tres de Febrero.☆10May 8, 2026Updated 2 weeks ago
- Verilog Code for I2C Protocol☆19Nov 12, 2020Updated 5 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Linux kernel module PPS Client Driver using OMAP Timer hardware☆18May 18, 2017Updated 9 years ago
- Radio Gyms is an open-source bundle of AI environments for radio communications.☆13May 10, 2022Updated 4 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Apr 9, 2020Updated 6 years ago
- soft color scheme for terminals with 256 colors☆17Aug 19, 2014Updated 11 years ago
- Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)☆46Jun 7, 2017Updated 8 years ago
- ☆18Jun 17, 2017Updated 8 years ago
- The simple, stupid and slow HNCP daemon☆19Jul 31, 2023Updated 2 years ago