secworks / aes

Related projects ⓘ

Alternatives and complementary repositories for aes

• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆490Updated 10 months ago
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆390Updated 3 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆518Updated this week
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆291Updated 2 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆438Updated 3 weeks ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆374Updated 4 months ago
• pnvamshi / Hardware-Implementation-of-AES-Verilog
  Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
  ☆37Updated 7 years ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆448Updated this week
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆214Updated last year
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆363Updated 4 months ago
• mematrix / AES-FPGA
  AES加密解密算法的Verilog实现
  ☆60Updated 8 years ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆297Updated this week
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆259Updated 4 years ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆288Updated 5 months ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆526Updated this week
• alexforencich / verilog-axis
  Verilog AXI stream components for FPGA implementation
  ☆745Updated 3 months ago
• pulp-platform / axi
  AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
  ☆1,113Updated last week
• subbdue / systemverilog.io
  Code used in
  ☆174Updated 7 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆251Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆371Updated 2 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆264Updated 6 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆199Updated 4 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆215Updated last year
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆171Updated last year
• alexforencich / verilog-uart
  Verilog UART
  ☆424Updated last year
• openhwgroup / cv32e40p
  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
  ☆966Updated 4 months ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆407Updated 2 weeks ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆452Updated 7 months ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆645Updated this week
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆243Updated 8 months ago