Alternatives and similar repositories for aes

Users that are interested in aes are comparing it to the libraries listed below

• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆457Updated 8 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆632Updated 9 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆414Updated 4 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆285Updated 5 years ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆706Updated this week
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆316Updated last month
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆568Updated 3 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆334Updated last year
• pnvamshi / Hardware-Implementation-of-AES-Verilog
  Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
  ☆41Updated 8 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆223Updated 5 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆258Updated 3 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆292Updated this week
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆355Updated 2 weeks ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆609Updated 3 weeks ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆558Updated 4 years ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆446Updated last year
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆447Updated 3 years ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆641Updated 2 weeks ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆653Updated this week
• lowRISC / style-guides
  lowRISC Style Guides
  ☆476Updated 3 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆310Updated 4 months ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆415Updated 7 years ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆539Updated last year
• subbdue / systemverilog.io
  Code used in
  ☆202Updated 8 years ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆488Updated this week
• dawsonjon / fpu
  synthesiseable ieee 754 floating point library in verilog
  ☆717Updated 2 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆145Updated 2 years ago
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆259Updated last year
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆192Updated last week
• pyuvm / pyuvm
  The UVM written in Python
  ☆499Updated last week