Alternatives and similar repositories for aes

Users that are interested in aes are comparing it to the libraries listed below

• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆439Updated 3 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆586Updated 4 months ago
• pnvamshi / Hardware-Implementation-of-AES-Verilog
  Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
  ☆40Updated 8 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆369Updated last year
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆653Updated 2 weeks ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆419Updated last year
• lowRISC / style-guides
  lowRISC Style Guides
  ☆450Updated 2 months ago
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆337Updated this week
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆278Updated last year
• Xilinx / XilinxTclStore
  Xilinx Tcl Store
  ☆368Updated this week
• chipsalliance / Cores-VeeR-EH2
  ☆244Updated 2 years ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆523Updated this week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆589Updated 2 weeks ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆511Updated 9 months ago
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆110Updated 3 years ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆296Updated this week
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆274Updated 5 years ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆508Updated 3 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆448Updated last month
• subbdue / systemverilog.io
  Code used in
  ☆194Updated 8 years ago
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆431Updated 3 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆217Updated 2 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆259Updated 12 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 5 years ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆600Updated 3 weeks ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆324Updated 8 months ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆174Updated 9 months ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆410Updated 6 years ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆139Updated last year
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆350Updated last week