Alternatives and similar repositories for aes

Users that are interested in aes are comparing it to the libraries listed below

• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆451Updated 7 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆310Updated last week
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆435Updated last year
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆352Updated 2 weeks ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆304Updated 3 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆615Updated 8 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆404Updated 3 months ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆692Updated 2 weeks ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆473Updated 2 months ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆281Updated 5 years ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆489Updated last week
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆554Updated 2 months ago
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆533Updated last year
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆556Updated this week
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆443Updated 3 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆336Updated last year
• RoaLogic / RV12
  RISC-V CPU Core
  ☆401Updated 6 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆253Updated 3 years ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆629Updated 2 weeks ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆631Updated 2 weeks ago
• pnvamshi / Hardware-Implementation-of-AES-Verilog
  Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
  ☆41Updated 8 years ago
• YosysHQ / sby
  SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows
  ☆483Updated last week
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆185Updated last year
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆126Updated 3 years ago
• ucb-bar / fpga-zynq
  Support for Rocket Chip on Zynq FPGAs
  ☆414Updated 6 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆235Updated 2 years ago
• subbdue / systemverilog.io
  Code used in
  ☆200Updated 8 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆264Updated 12 years ago
• IObundle / iob-cache
  Verilog Configurable Cache
  ☆187Updated 2 weeks ago
• veripool / verilog-perl
  Verilog parser, preprocessor, and related tools for the Verilog-Perl package
  ☆144Updated last year