Alternatives and similar repositories for AES-Processor:

Users that are interested in AES-Processor are comparing it to the libraries listed below

• govindjeevan / Weighted-Round-Robin-Arbiter
  Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components
  ☆18Updated 7 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆11Updated 4 years ago
• emmanouil-komninos / jtag_vip_uvm
  ☆12Updated 9 years ago
• alice820621 / A-UVM-verification-for-DAC-and-ADC-model-with-APB-BFM
  A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…
  ☆15Updated 6 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆19Updated last month
• xdesigns / 4way-cache
  Verilog cache implementation of 4-way FIFO 16k Cache
  ☆19Updated 12 years ago
• PacoReinaCampo / SoC-DV
  System on Chip verified with UVM/OSVVM/FV
  ☆24Updated last month
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆20Updated 3 years ago
• praveenkhemalapure / DDR3-controller-verification
  DDR3 function verification environment in UVM
  ☆23Updated 6 years ago
• avashist003 / FIFO_SystemVerilog_Assertion
  Synchronous FIFO design & verification using systemVerilog Assertions
  ☆15Updated 3 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆27Updated 4 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 5 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆33Updated 8 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆31Updated 2 years ago
• alice820621 / SystemVerilog-Implementation-of-DDR3-Controller
  The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…
  ☆21Updated 6 years ago
• panweitao / riscvv
  an open source uvm verification platform for e200 (riscv)
  ☆26Updated 6 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆41Updated 5 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 3 years ago
• bvnirliptha / AMBA-3-AHB--LITE-Protocol-Design-and-Verification
  -Designed and Verified a Bus Functional Model of AHB-LITE Protocol from scratch. -Developed Assertion based verification IP to verify the…
  ☆21Updated 9 years ago
• forever-gk / AHB-SystemVerilog
  ☆17Updated 9 years ago
• Gateway91 / AHB-APB_Bridge_UVM_Env
  AHB-APB UVM Verification Environment
  ☆17Updated 9 years ago
• wanderingnail / AXI_DMA
  ☆19Updated 2 years ago
• amamory-verification / uvm-basics
  my UVM training projects
  ☆32Updated 6 years ago
• samy-maxvy / MAXVY_MIPI_I3C_Basic_Master_Controller_IP
  It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.
  ☆16Updated 5 years ago
• open-dv / dma_axi
  ☆16Updated 5 years ago
• ljgibbslf / basic_cache_core
  ☆26Updated 4 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆20Updated 8 months ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆28Updated last month
• muzafferkal / axi-bfm
  AXI3 Bus Functional Models (Initiator & Target)
  ☆28Updated 2 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 10 months ago