kinap / AES-ProcessorLinks
AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.
☆17Updated 8 years ago
Alternatives and similar repositories for AES-Processor
Users that are interested in AES-Processor are comparing it to the libraries listed below
Sorting:
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Updated 7 years ago
- Contains commonly used UVM components (agents, environments and tests).☆32Updated 7 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆19Updated 6 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 7 years ago
- an open source uvm verification platform for e200 (riscv)☆29Updated 7 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated last week
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆20Updated 8 years ago
- ☆13Updated 10 years ago
- ☆31Updated 5 years ago
- UVM resource from github, run simulation use YASAsim flow☆33Updated 5 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Updated 3 years ago
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Updated 13 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- DDR3 function verification environment in UVM☆26Updated 7 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆17Updated 4 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 4 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 5 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆67Updated 9 years ago
- systemc建模相关☆28Updated 11 years ago
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- ☆27Updated 4 years ago
- ☆10Updated 2 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- Direct Access Memory for MPSoC☆13Updated last week
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆42Updated 6 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- Implementation of the PCIe physical layer☆60Updated 6 months ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Updated 7 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆10Updated 8 years ago