kinap / AES-ProcessorLinks
AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.
☆16Updated 8 years ago
Alternatives and similar repositories for AES-Processor
Users that are interested in AES-Processor are comparing it to the libraries listed below
Sorting:
- ☆14Updated 5 years ago
- SoC Based on ARM Cortex-M3☆32Updated last month
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆17Updated 5 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- EE 260 Winter 2017: Advanced VLSI Design☆64Updated 8 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆31Updated last month
- System on Chip verified with UVM/OSVVM/FV☆28Updated last month
- Network on Chip for MPSoC☆26Updated last month
- Verification IP for Watchdog☆11Updated 4 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago
- -Designed and Verified a Bus Functional Model of AHB-LITE Protocol from scratch. -Developed Assertion based verification IP to verify the…☆21Updated 9 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆12Updated 5 years ago
- ☆13Updated 10 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 12 years ago
- my UVM training projects☆34Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- SystemVerilog testbench for an Ethernet 10GE MAC core☆45Updated 9 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede …☆22Updated 6 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 6 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 4 months ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆44Updated last year
- Generate a Verilog Source file and testbench file for a given Moore FSM☆17Updated 12 years ago
- ☆20Updated 2 years ago
- ☆12Updated 9 years ago
- ☆17Updated 10 years ago