C++ and Verilog to implement AES128
☆24Apr 30, 2018Updated 7 years ago
Alternatives and similar repositories for AES128
Users that are interested in AES128 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.☆17Dec 16, 2017Updated 8 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Dec 10, 2021Updated 4 years ago
- ☆27Feb 27, 2021Updated 5 years ago
- AES-based-on-FPGA developed by verilog.☆23Apr 23, 2020Updated 5 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 6 years ago
- AES-128 Encryption☆10Jul 17, 2014Updated 11 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆42Jun 4, 2017Updated 8 years ago
- Advanced encryption standard implementation in verilog.☆31Oct 2, 2022Updated 3 years ago
- This project contains synthesized verilog codes for Encryption/Decryption of secure IP stream using Advanced Encryption Standard (AES) al…☆17May 2, 2013Updated 12 years ago
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…☆17Mar 22, 2017Updated 9 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Apr 15, 2021Updated 4 years ago
- Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…☆421Dec 29, 2025Updated 2 months ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 5 years ago
- SMPP client library☆15Mar 17, 2026Updated last week
- Design & Implementation of Multi Clock Domain System using Verilog HDL☆13Oct 4, 2023Updated 2 years ago
- Edge Impulse firmware for Nordic Thingy91☆13Updated this week
- AES implementation on FPGA☆13Apr 17, 2016Updated 9 years ago
- Verilog implementation of Pac-Man made for a class's final project☆19Mar 7, 2012Updated 14 years ago
- AES implementation in MATLAB☆12Nov 15, 2016Updated 9 years ago
- Repository for the course "Sensor Fusion and Non-Linear Filtering" - SSY345 at Chalmers University of Technology☆13May 19, 2019Updated 6 years ago
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆14May 11, 2014Updated 11 years ago
- Using an Altera DE10-Lite FPGA development board to simulate an FFT processor. Audio input frequencies will be visualized onto a VGA disp…☆15May 5, 2020Updated 5 years ago
- LeNet-5 use c achieve☆13Jan 10, 2020Updated 6 years ago
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- Golang package for PCI Express data transfers☆13Apr 24, 2018Updated 7 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆11Sep 30, 2020Updated 5 years ago
- SystemVerilog examples and projects☆20Jun 10, 2025Updated 9 months ago
- ☆18Jul 11, 2021Updated 4 years ago
- ☆18May 1, 2024Updated last year
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- Open source SDR LTE software suite from Software Radio Systems (SRS)☆14Sep 6, 2019Updated 6 years ago
- ☆11Aug 2, 2023Updated 2 years ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆13Mar 5, 2017Updated 9 years ago
- Minimal startup code + Makefile for building bare-metal C programs for Cortex-M4☆11Jul 26, 2016Updated 9 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- Advanced Machine Learning and Signal Processing IBM☆18Sep 6, 2019Updated 6 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆18Jan 27, 2023Updated 3 years ago