C++ and Verilog to implement AES128
☆24Apr 30, 2018Updated 8 years ago
Alternatives and similar repositories for AES128
Users that are interested in AES128 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.☆19Dec 16, 2017Updated 8 years ago
- ☆27Feb 27, 2021Updated 5 years ago
- AES-based-on-FPGA developed by verilog.☆22Apr 23, 2020Updated 6 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆42Jun 4, 2017Updated 9 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- AES-128 Encryption☆11Jul 17, 2014Updated 12 years ago
- Advanced encryption standard implementation in verilog.☆31Oct 2, 2022Updated 4 years ago
- This project contains synthesized verilog codes for Encryption/Decryption of secure IP stream using Advanced Encryption Standard (AES) al…☆17May 2, 2013Updated 13 years ago
- AES☆16Oct 4, 2022Updated 4 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆23Apr 15, 2021Updated 5 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 6 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆148Jul 31, 2022Updated 4 years ago
- Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…☆464Dec 29, 2025Updated 9 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Design & Implementation of Multi Clock Domain System using Verilog HDL☆13Oct 4, 2023Updated 3 years ago
- AES implementation on FPGA☆13Apr 17, 2016Updated 10 years ago
- Verilog implementation of Pac-Man made for a class's final project☆19Mar 7, 2012Updated 14 years ago
- AES implementation in MATLAB☆12Nov 15, 2016Updated 9 years ago
- Repository for the course "Sensor Fusion and Non-Linear Filtering" - SSY345 at Chalmers University of Technology☆14May 19, 2019Updated 7 years ago
- TA's implementation for the project of Computer Architecture and Intelligent Chip Design (23 Spring)☆10May 20, 2023Updated 3 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆17Jun 24, 2020Updated 6 years ago
- LeNet-5 use c achieve☆13Jan 10, 2020Updated 6 years ago
- AES加密解密算法的Verilog实现☆71Jan 17, 2016Updated 10 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆12Oct 8, 2021Updated 5 years ago
- Using an Altera DE10-Lite FPGA development board to simulate an FFT processor. Audio input frequencies will be visualized onto a VGA disp…☆17May 5, 2020Updated 6 years ago
- FIR band-pass filter using Verilog HDL.☆14Sep 7, 2026Updated last month
- yolov5-acceleration-fpga☆11Jun 25, 2025Updated last year
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆12Sep 30, 2020Updated 6 years ago
- SystemVerilog examples and projects☆21Jun 10, 2025Updated last year
- Studies on basic hardware and software edge detection algorithms for future Stochastic Computing applications☆10Jul 11, 2021Updated 5 years ago
- ☆18Jul 11, 2021Updated 5 years ago
- ☆18May 1, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Digital Systems Course Project: Fake Currency Detection in Verilog using Basys3 FPGA and MATLAB☆10Sep 30, 2020Updated 6 years ago
- Advanced Machine Learning and Signal Processing IBM☆17Sep 6, 2019Updated 7 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆20Jan 27, 2023Updated 3 years ago
- Open source SDR LTE software suite from Software Radio Systems (SRS)☆14Sep 6, 2019Updated 7 years ago
- Open5GS is a C-language Open Source implementation of the 3GPP Evolved Packet Core, i.e. the core network of an LTE network.☆10Jul 19, 2026Updated 2 months ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 7 years ago
- ☆11Oct 10, 2019Updated 7 years ago