Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
☆17Oct 8, 2020Updated 5 years ago
Alternatives and similar repositories for modexp
Users that are interested in modexp are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆37Sep 25, 2014Updated 11 years ago
- ☆12Aug 26, 2016Updated 9 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Feb 21, 2024Updated 2 years ago
- 4096bit RSA project, with verilog code, python test code, etc☆47Oct 8, 2019Updated 6 years ago
- Implementation of RSA algorithm on FPGA using Verilog☆27Aug 1, 2018Updated 7 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆13Apr 24, 2015Updated 11 years ago
- VHDL implementation of RSA encryption/decryption using Montgomery modular multipliers☆24Apr 15, 2016Updated 10 years ago
- Partial Verilog implimentation of a WiMAX OFDM Phy☆19May 28, 2012Updated 14 years ago
- Verilog implementation of the SHA-512 hash function.☆46Jan 17, 2026Updated 4 months ago
- open cv software isp study☆18Nov 9, 2020Updated 5 years ago
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆27Mar 11, 2022Updated 4 years ago
- Verilog 2001 implementation of the ChaCha stream cipher.☆45Jan 17, 2026Updated 4 months ago
- Library of generic verilog buildingblocks☆17Dec 25, 2025Updated 5 months ago
- USB capture IP☆26Jun 6, 2020Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆14Nov 26, 2024Updated last year
- Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board.☆16Oct 16, 2018Updated 7 years ago
- CMSIS Pack for the mbedTLS software stack☆25Feb 5, 2026Updated 4 months ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- FM receiving and broadcasting; Real-time duplexing; Scarborough Fair☆15Dec 6, 2019Updated 6 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆35May 12, 2020Updated 6 years ago
- Implementation of the SHA256 Algorithm in Verilog☆39Jan 2, 2012Updated 14 years ago
- A Voila-Jones face detector hardware implementation☆33Nov 29, 2018Updated 7 years ago
- Implementation of the PCIe physical layer☆63Jul 11, 2025Updated 11 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Verilog FPGA code : including experimental DSP audio processor☆13Dec 1, 2020Updated 5 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- An optimized C implementation of the RSA public key encryption using the Montgomery Multiplication algorithm☆18Jan 16, 2020Updated 6 years ago
- Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. …☆15Jan 19, 2018Updated 8 years ago
- Implementation of the CMAC keyed hash function using AES as block cipher.☆16Apr 2, 2025Updated last year
- The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)☆10Jan 9, 2016Updated 10 years ago
- Benchmarks for High-Level Synthesis☆11Mar 17, 2023Updated 3 years ago
- Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…☆448Dec 29, 2025Updated 5 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Jupyterlab extension containing a UI for debugging☆10Dec 2, 2019Updated 6 years ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- hdmi-ts Project☆13Jun 11, 2017Updated 9 years ago
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆16Sep 25, 2024Updated last year
- Mathematical Functions in Verilog☆98Mar 7, 2021Updated 5 years ago
- A Hardware MD5 Cracker for the Cyclone V SoC☆12Mar 25, 2015Updated 11 years ago
- A VHDL implementation of 128 bit AES encryption with a PCIe interface.☆27Jan 9, 2017Updated 9 years ago