Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
☆17Oct 8, 2020Updated 6 years ago
Alternatives and similar repositories for modexp
Users that are interested in modexp are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆37Sep 25, 2014Updated 12 years ago
- a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier☆29Mar 11, 2022Updated 4 years ago
- Implementation of RSA algorithm on FPGA using Verilog☆27Aug 1, 2018Updated 8 years ago
- 4096bit RSA project, with verilog code, python test code, etc☆47Oct 8, 2019Updated 7 years ago
- ☆14Aug 26, 2016Updated 10 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- VHDL implementation of RSA encryption/decryption using Montgomery modular multipliers☆24Apr 15, 2016Updated 10 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Feb 21, 2024Updated 2 years ago
- personal practice☆11Sep 18, 2026Updated last month
- Partial Verilog implimentation of a WiMAX OFDM Phy☆19May 28, 2012Updated 14 years ago
- Tools for testing kernel ciphers and hash algorithm☆15Apr 27, 2023Updated 3 years ago
- open cv software isp study☆18Nov 9, 2020Updated 5 years ago
- Verilog implementation of the SHA-512 hash function.☆47Jan 17, 2026Updated 9 months ago
- Verilog 2001 implementation of the ChaCha stream cipher.☆47Jan 17, 2026Updated 9 months ago
- Library of generic verilog buildingblocks☆18Dec 25, 2025Updated 10 months ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Implementation of SHA256 Hasher with UART Transceiver in Verilog. Designed to run on Altera's DE2 FPGA Development Board.☆16Oct 16, 2018Updated 8 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- TMR utilities for the SpyDrNet project☆16Nov 7, 2023Updated 2 years ago
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆14Nov 26, 2024Updated last year
- The OpenCpuX API☆10Jun 26, 2026Updated 4 months ago
- The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)☆10Jan 9, 2016Updated 10 years ago
- FM receiving and broadcasting; Real-time duplexing; Scarborough Fair☆15Dec 6, 2019Updated 6 years ago
- ☆23Dec 7, 2019Updated 6 years ago
- USB -> AXI Debug Bridge☆47Jun 5, 2021Updated 5 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- USB capture IP☆27Jun 6, 2020Updated 6 years ago
- An optimized C implementation of the RSA public key encryption using the Montgomery Multiplication algorithm☆19Jan 16, 2020Updated 6 years ago
- A Voila-Jones face detector hardware implementation☆33Nov 29, 2018Updated 7 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/x393☆40Mar 16, 2023Updated 3 years ago
- MMC (and derivative standards) host controller☆26Sep 14, 2020Updated 6 years ago
- Jupyterlab extension containing a UI for debugging☆10Dec 2, 2019Updated 6 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆37May 12, 2020Updated 6 years ago
- Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. …☆15Jan 19, 2018Updated 8 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Verilog FPGA code : including experimental DSP audio processor☆14Dec 1, 2020Updated 5 years ago
- Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…☆471Dec 29, 2025Updated 10 months ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆16Sep 25, 2024Updated 2 years ago
- Implementation of the CMAC keyed hash function using AES as block cipher.☆18Apr 2, 2025Updated last year
- RSA string encrypter and decrypter☆13Sep 2, 2018Updated 8 years ago