PrincetonUniversity / IMDb-Archive
ILA Model Database
☆22Updated 4 years ago
Alternatives and similar repositories for IMDb-Archive:
Users that are interested in IMDb-Archive are comparing it to the libraries listed below
- A hardware synthesis framework with multi-level paradigm☆38Updated 3 months ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆58Updated 6 months ago
- CGRA Compilation Framework☆83Updated last year
- ☆91Updated last year
- Benchmarks for Accelerator Design and Customized Architectures☆121Updated 5 years ago
- CGRA framework with vectorization support.☆29Updated 2 weeks ago
- ☆86Updated last year
- ☆58Updated this week
- A Modeling and Verification Platform for SoCs using ILAs☆76Updated 10 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆49Updated last year
- ☆25Updated last year
- ☆15Updated 2 years ago
- ☆40Updated 3 months ago
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆71Updated 6 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆52Updated 5 years ago
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated last year
- EQueue Dialect☆40Updated 3 years ago
- ☆57Updated last year
- Release of stream-specialization software/hardware stack.☆121Updated 2 years ago
- DASS HLS Compiler☆29Updated last year
- The OpenPiton Platform☆28Updated last year
- The Chronos FPGA Framework to accelerate ordered applications☆22Updated 4 years ago
- Tests for example Rocket Custom Coprocessors☆74Updated 5 years ago
- ☆15Updated 2 years ago
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆64Updated 10 months ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆24Updated 7 months ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- CoreIR Symbolic Analyzer☆72Updated 4 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆59Updated 2 months ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆68Updated last week