PrincetonUniversity / IMDb-ArchiveLinks
ILA Model Database
☆23Updated 5 years ago
Alternatives and similar repositories for IMDb-Archive
Users that are interested in IMDb-Archive are comparing it to the libraries listed below
Sorting:
- A Modeling and Verification Platform for SoCs using ILAs☆77Updated last year
- DASS HLS Compiler☆29Updated 2 years ago
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆54Updated 5 years ago
- ☆87Updated last year
- ☆29Updated 8 years ago
- ☆13Updated 5 years ago
- The OpenPiton Platform☆28Updated 2 years ago
- Fast Symbolic Repair of Hardware Design Code☆26Updated 8 months ago
- CoreIR Symbolic Analyzer☆74Updated 4 years ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆50Updated 2 years ago
- ☆19Updated last year
- ☆13Updated 4 years ago
- ☆61Updated last week
- A hardware synthesis framework with multi-level paradigm☆41Updated 8 months ago
- ☆16Updated 2 years ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 6 years ago
- ☆103Updated 3 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆89Updated last year
- ☆58Updated 2 years ago
- Next generation CGRA generator☆114Updated this week
- Implementation of the Advanced Encryption Standard in Chisel☆19Updated 3 years ago
- ☆23Updated 4 years ago
- ☆17Updated 4 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 8 years ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆22Updated 3 months ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆16Updated 6 years ago
- LLM Evaluation Benchmark on Hardware Formal Verification☆30Updated 6 months ago
- Equivalence checking with Yosys☆46Updated last week
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆115Updated 4 months ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆20Updated 11 months ago