Alternatives and similar repositories for svck

Users that are interested in svck are comparing it to the libraries listed below

• snishizawa / libretto
  Characterizer
  ☆30Updated 3 weeks ago
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆53Updated 2 months ago
• Coloquinte / moosic-yosys-plugin
  Yosys plugin for logic locking and supply-chain security
  ☆22Updated 4 months ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 3 months ago
• byuccl / bfat
  Bitstream Fault Analysis Tool
  ☆14Updated 2 years ago
• fossi-foundation / ciel
  Open-source PDK version manager
  ☆22Updated 2 weeks ago
• pulp-platform / artistic
  An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
  ☆18Updated last month
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago
• iic-jku / SKY130_SAR-ADC1
  Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
  ☆42Updated 5 months ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• pulp-platform / svase
  ☆32Updated 7 months ago
• RTimothyEdwards / capiche
  Parasitic capacitance analysis of foundry metal stackups
  ☆15Updated 3 months ago
• growly / bfg
  An Open-Source Silicon Compiler for Reduced-Complexity Reconfigurable Fabrics
  ☆11Updated last week
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• diadatp / sky130_rf_tools
  Guides and templates for using open source RF design tools with the SkyWater SKY130 process.
  ☆19Updated 4 years ago
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• iic-jku / IIC-RALF
  Reinforcement learning assisted analog layout design flow.
  ☆29Updated last year
• chili-chips-ba / openPCIE
  Peripheral Component Interconnect has taken Express lane long ago, going for xGbps SerDes. Now (for the first time) in opensource on the …
  ☆16Updated last week
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆23Updated this week
• efabless / caravel_mgmt_soc_litex
  https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/
  ☆28Updated 7 months ago
• mortbopet / NetCracker
  NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between…
  ☆17Updated 4 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆54Updated last year
• vsdip / vsdsram_sky130
  ☆42Updated 3 years ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆25Updated 4 years ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆39Updated last month
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated this week
• schang412 / cocotbext-spi
  ☆24Updated 4 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 4 months ago