comsec-group / cascade-artifactsLinks
Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)
☆138Updated last year
Alternatives and similar repositories for cascade-artifacts
Users that are interested in cascade-artifacts are comparing it to the libraries listed below
Sorting:
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆78Updated 2 months ago
- ☆101Updated last year
- rfuzz: coverage-directed fuzzing for RTL research platform☆113Updated 3 years ago
- Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation☆49Updated 9 months ago
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆95Updated this week
- ☆88Updated 3 years ago
- Code repository for Coppelia tool☆23Updated 5 years ago
- Student Starter Code for Secure Hardware Design at MIT☆87Updated last week
- Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"☆31Updated 7 months ago
- Fuzz everything! Now let's fuzz chip!☆31Updated last week
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆17Updated 4 years ago
- Medusa Repository: Transynther tool and Medusa Attack☆23Updated 5 years ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆68Updated 6 years ago
- ☆25Updated 2 years ago
- All the tools you need to reproduce the CellIFT paper experiments☆23Updated 11 months ago
- Pre-Silicon Hardware Fuzzing Toolkit☆60Updated 5 months ago
- This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.☆57Updated 6 years ago
- HW interface for memory caches☆28Updated 5 years ago
- RISC-V Security Model☆34Updated last week
- SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs (ICCAD 2023)☆23Updated last year
- Revizor - Hardware fuzzing for the age of speculation☆180Updated 2 weeks ago
- A port of the RIPE suite to RISC-V.☆29Updated 7 years ago
- Open-source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)☆33Updated 10 months ago
- ☆17Updated 3 years ago
- Using Data Memory-Dependent Prefetchers to Leak Data at Rest☆38Updated 3 years ago
- TikTag: Breaking ARM's Memory Tagging Extension with Speculative Execution (IEEE S&P 2025)☆85Updated last year
- The code in this project demonstrates 2 novel Spectre-V4 attacks, named as out-of-place Spectre-STL and Spectre-CTL, based on the Specula…☆22Updated 2 years ago
- This repository contains the hardware, software, and OS support for the Programmable Hardware Monitor (PHMon).☆27Updated 5 years ago
- Artefacts for: "VMScape: Exposing and Exploiting Incomplete Branch Predictor Isolation in Cloud Environments"☆36Updated 3 months ago
- ARCHIE is a QEMU-based architecture-independent fault evaluation tool, that is able to simulate transient and permanent instruction and d…☆33Updated last month