comsec-group / cascade-artifactsLinks
Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)
☆138Updated last year
Alternatives and similar repositories for cascade-artifacts
Users that are interested in cascade-artifacts are comparing it to the libraries listed below
Sorting:
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆78Updated 2 months ago
- rfuzz: coverage-directed fuzzing for RTL research platform☆113Updated 3 years ago
- ☆101Updated last year
- Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation☆49Updated 9 months ago
- ☆88Updated 3 years ago
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆95Updated last week
- Medusa Repository: Transynther tool and Medusa Attack☆23Updated 5 years ago
- Code repository for Coppelia tool☆23Updated 5 years ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆17Updated 4 years ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆68Updated 6 years ago
- ☆25Updated 2 years ago
- Open-source release of "Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud" (ASPLOS '24)☆33Updated 10 months ago
- Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"☆31Updated 7 months ago
- Student Starter Code for Secure Hardware Design at MIT☆86Updated 2 weeks ago
- Revizor - Hardware fuzzing for the age of speculation☆180Updated last week
- A port of the RIPE suite to RISC-V.☆29Updated 7 years ago
- All the tools you need to reproduce the CellIFT paper experiments☆23Updated 11 months ago
- Pre-Silicon Hardware Fuzzing Toolkit☆60Updated 5 months ago
- RISC-V Security Model☆34Updated this week
- Fuzz everything! Now let's fuzz chip!☆31Updated last week
- HW interface for memory caches☆28Updated 5 years ago
- Automatic detection of speculative information flows☆75Updated 4 years ago
- Using Data Memory-Dependent Prefetchers to Leak Data at Rest☆38Updated 3 years ago
- This repository contains the hardware, software, and OS support for the Programmable Hardware Monitor (PHMon).☆27Updated 5 years ago
- Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser☆62Updated 3 years ago
- Proof-of-concept implementation for the paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21)☆65Updated 8 months ago
- ☆17Updated 3 years ago
- Project Repo for the Simulator Independent Coverage Research☆21Updated 2 years ago
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Updated 4 years ago
- This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.☆57Updated 6 years ago