comsec-group / cascade-artifacts
Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)
☆124Updated 6 months ago
Alternatives and similar repositories for cascade-artifacts:
Users that are interested in cascade-artifacts are comparing it to the libraries listed below
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆60Updated 7 months ago
- This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. …☆86Updated last month
- rfuzz: coverage-directed fuzzing for RTL research platform☆103Updated 2 years ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆14Updated 3 years ago
- ☆80Updated 9 months ago
- ☆80Updated 2 years ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆61Updated 5 years ago
- ☆23Updated 2 years ago
- Medusa Repository: Transynther tool and Medusa Attack☆21Updated 4 years ago
- Code repository for Coppelia tool☆22Updated 4 years ago
- A port of the RIPE suite to RISC-V.☆29Updated 6 years ago
- Student Starter Code for Secure Hardware Design at MIT☆43Updated 9 months ago
- Proof-of-concept implementation for the paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21)☆56Updated 3 years ago
- RISC-V Security Model☆30Updated last week
- Proof-of-concept implementation for the paper "(M)WAIT for It: Bridging the Gap between Microarchitectural and Architectural Side Channel…☆25Updated last year
- ☆18Updated 2 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆32Updated 3 years ago
- Project Repo for the Simulator Independent Coverage Research☆18Updated 2 years ago
- HW interface for memory caches☆26Updated 4 years ago
- Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation☆25Updated last year
- A concolic testing engine for RISC-V embedded software with support for SystemC peripherals☆22Updated last year
- HW Design Collateral for Caliptra RoT IP☆84Updated this week
- A tool to enable fuzzing for Spectre vulnerabilities☆30Updated 5 years ago
- ☆60Updated last month
- Using Data Memory-Dependent Prefetchers to Leak Data at Rest☆35Updated 2 years ago
- Machine-readable database of the RISC-V specification, and tools to generate various views☆46Updated this week
- Medusa Repository: Transynther tool and Medusa Attack☆20Updated 4 years ago
- All the tools you need to reproduce the CellIFT paper experiments☆18Updated last month
- This repository contains the hardware, software, and OS support for the Programmable Hardware Monitor (PHMon).☆26Updated 4 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆47Updated last week