Alternatives and similar repositories for simulator-independent-coverage

Users that are interested in simulator-independent-coverage are comparing it to the libraries listed below

• ekiwi / rfuzz
  rfuzz: coverage-directed fuzzing for RTL research platform
  ☆112Updated 3 years ago
• gipsyh / rIC3
  Hardware Formal Verification Tool
  ☆76Updated this week
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆36Updated 4 years ago
• hackdac / hackdac_2018_beta
  The SoC used for the beta phase of Hack@DAC 2018.
  ☆18Updated 5 years ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 5 years ago
• HWSec-UNC / Sylvia
  ☆18Updated 6 months ago
• hkustgz-zhang-lab / HW-Formal-Paper
  Recent papers related to hardware formal verification.
  ☆75Updated 2 years ago
• zilongwang123 / LeaVe
  A tool for checking the contract satisfaction for hardware designs
  ☆11Updated last month
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆99Updated this week
• compsec-snu / specdoctor
  ☆25Updated 2 years ago
• compsec-snu / difuzz-rtl
  ☆100Updated last year
• shioya-lab-public / surgefuzz
  SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs (ICCAD 2023)
  ☆22Updated last year
• efeslab / asplos22-hardware-debugging-artifact
  ☆13Updated last year
• dian-lun-lin / GenFuzz
  GPU-enabled Hardware Fuzzer using Genetic Algorithm
  ☆19Updated 2 years ago
• hammad-a / verilog_repair
  Automated Repair of Verilog Hardware Descriptions
  ☆35Updated 11 months ago
• sycuricon / MorFuzz
  Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation
  ☆47Updated 8 months ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆81Updated last year
• comsec-group / encarsia
  ☆26Updated 8 months ago
• efeslab / hardware-bugbase
  ☆20Updated last year
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆74Updated 5 years ago
• pfnet-research / ATPG4SV
  A prototype of Concolic Testing engine for SystemVerilog, developed as part of PFN summer internship 2018.
  ☆19Updated 7 years ago
• comsec-group / cellift-meta
  All the tools you need to reproduce the CellIFT paper experiments
  ☆23Updated 10 months ago
• OpenXiangShan / xfuzz
  Fuzzing General-Purpose Hardware Designs with Software Fuzzers
  ☆24Updated last month
• googleinterns / hw-fuzzing
  ☆87Updated 2 years ago
• Gy-Hu / HWMCC24-benchmark
  Collection for submission (Hardware Model Checking Benchmark)
  ☆11Updated last month
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆34Updated 8 months ago
• iscas-tis / ChiRVFormal
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆16Updated 6 months ago
• cascade-artifacts-designs / cascade-meta
  ☆12Updated 8 months ago
• makaimann / ride-core-demo
  A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
  ☆12Updated 6 years ago
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆68Updated 6 years ago