Alternatives and similar repositories for nerv:

Users that are interested in nerv are comparing it to the libraries listed below

• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆80Updated last week
• SymbioticEDA / getting-started-FV
  ☆18Updated 4 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• phanrahan / mantle
  mantle library
  ☆43Updated 2 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 3 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆45Updated 8 months ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆40Updated last year
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆33Updated last week
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆47Updated 2 months ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆55Updated 5 months ago
• Kuree / kratos
  Debuggable hardware generator
  ☆68Updated 2 years ago
• dh73 / A_Formal_Tale_Chapter_I_AMBA
  AXI Formal Verification IP
  ☆20Updated 3 years ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated this week
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆40Updated 3 months ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆38Updated last year
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆43Updated 2 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 5 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆32Updated last year
• litex-hub / pythondata-cpu-rocket
  Python module containing verilog files for rocket cpu (for use with LiteX).
  ☆13Updated 2 months ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year