Alternatives and similar repositories for picorv32_Xilinx

Users that are interested in picorv32_Xilinx are comparing it to the libraries listed below

• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆74Updated 3 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 10 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆96Updated 6 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆58Updated 8 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆90Updated last year
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 11 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆89Updated 3 years ago
• cjhonlyone / NandFlashController
  AXI Interface Nand Flash Controller (Sync mode)
  ☆96Updated last year
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆65Updated 5 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆37Updated 3 years ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆153Updated last year
• WangXuan95 / FPGA-MPEG2-encoder
  An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器，可实现视频压缩。
  ☆132Updated last year
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆107Updated 2 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆106Updated 4 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆121Updated 11 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆77Updated 13 years ago
• ForrestBlue / cortexm0ds
  ☆68Updated 9 years ago
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆35Updated 5 years ago
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆123Updated 2 years ago
• wudayemen / gen_apb_file
  ☆72Updated 4 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• maxs-well / Ethernet-design-verilog
  Gigabit Ethernet UDP communication driver
  ☆79Updated 6 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆103Updated 5 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆139Updated last year
• WangXuan95 / FPGA-Gzip-compressor
  An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …
  ☆136Updated last year
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 5 years ago
• tastynoob / ritter-soc
  a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog
  ☆23Updated 2 years ago
• flyjancy / CortexM0_SoC_Task
  Step by step tutorial for building CortexM0 SoC
  ☆38Updated 3 years ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆210Updated last year