A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
☆80Jun 10, 2021Updated 5 years ago
Alternatives and similar repositories for picorv32_Xilinx
Users that are interested in picorv32_Xilinx are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 4096bit Iterative digit-digit Montgomery Multiplication in Verilog☆20Apr 18, 2022Updated 4 years ago
- Gigabit Ethernet UDP communication driver☆87Jul 26, 2019Updated 7 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆42Oct 16, 2017Updated 9 years ago
- Simple demo showing how to use the ping pong FIFO☆17May 2, 2016Updated 10 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- a MIPS-based embedded system on FPGA☆10Mar 10, 2017Updated 9 years ago
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 6 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Jul 17, 2014Updated 12 years ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,395Sep 7, 2026Updated last month
- SystemVerilog implementation of a Dynamically Weighted Round Robin arbiter☆14Mar 21, 2017Updated 9 years ago
- Implementation of the PCIe physical layer☆64Jul 11, 2025Updated last year
- High-througput logic analyzer for FPGA☆17Oct 8, 2020Updated 6 years ago
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Oct 19, 2026Updated last week
- Secure and Fast FPGA-based Hardware Scheduler for Accelerating Task Scheduling in Multi-core Systems☆13Apr 25, 2023Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 基于FPGA的循迹小车☆12Nov 20, 2021Updated 4 years ago
- Porting PicoRV32 to Artix-7 and Spartan-7. Generic vivado template for supported Xilinx FPGA is included.☆45Nov 13, 2024Updated last year
- A Vivado IP package of the PicoRV32 RISC-V processor☆16Jul 9, 2020Updated 6 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆58May 10, 2021Updated 5 years ago
- axi video dma ip in verilog☆11Aug 22, 2020Updated 6 years ago
- A simple UVM project. The DUT(RTL) is a simple amplifier.☆10Sep 28, 2022Updated 4 years ago
- an open source uvm verification platform for e200 (riscv)☆31May 5, 2018Updated 8 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆56Jan 19, 2021Updated 5 years ago
- verilog/FPGA hardware description for very simple GPU☆17Apr 9, 2019Updated 7 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Build an open source, extremely simple DMA.☆25Feb 17, 2019Updated 7 years ago
- ☆27Nov 4, 2022Updated 3 years ago
- Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核☆28Dec 17, 2022Updated 3 years ago
- turbo 8051☆31Aug 30, 2017Updated 9 years ago
- Convolutional Neural Networks Coprocessor☆12Dec 8, 2022Updated 3 years ago
- The project is a simple example about how to use TensorFlow to train a ConNet model from labeled dataset and then use Vitis AI tools to d…☆16Aug 15, 2020Updated 6 years ago
- This repository provides a method to dynamically change the clock output frequency, phase shift, and duty cycle of the mixed-mode clock m…☆16Nov 4, 2020Updated 5 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆24Jul 20, 2023Updated 3 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆31Apr 25, 2016Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs☆11Jun 19, 2020Updated 6 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 8 years ago
- ☆28Jun 21, 2024Updated 2 years ago
- digital recognition base on FPGA☆12Nov 10, 2019Updated 6 years ago
- ☆20Jun 5, 2018Updated 8 years ago
- Raptor end-to-end FPGA Compiler and GUI☆101Dec 11, 2024Updated last year
- Generic AHB master stub☆12Jul 17, 2014Updated 12 years ago