Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.
☆13May 5, 2015Updated 10 years ago
Alternatives and similar repositories for UART_ECHO
Users that are interested in UART_ECHO are comparing it to the libraries listed below
Sorting:
- Verilog Package for Sublime Text 2/3☆23Jan 27, 2024Updated 2 years ago
- ☆12Feb 20, 2026Updated last week
- playful-turtle USB gamepad firmware for the seeeduino xiao☆10Jul 19, 2023Updated 2 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Jun 8, 2017Updated 8 years ago
- python_learning☆15May 18, 2022Updated 3 years ago
- ☆13Jan 23, 2024Updated 2 years ago
- 基于Qt qwt的串口示波器☆12May 8, 2019Updated 6 years ago
- STM32 Hiperface Encoder circuit and software☆11Nov 14, 2023Updated 2 years ago
- Record and replay serial port traffic with pytest.☆10Dec 30, 2025Updated 2 months ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- An Arduino library for decoding multiple RC protocols.☆15Sep 2, 2025Updated 6 months ago
- 适用于FPGA——利用串口通信接收幅度频率信息数据帧,控制DA输出相应正弦信号☆10Jul 10, 2019Updated 6 years ago
- A python GUI that plots serial data in real time. Used with embedded systems. Uses matplotlib and pyserial☆83Apr 28, 2016Updated 9 years ago
- 基于Verilog实现的串口发送程序,带奇偶校验位。☆12Aug 23, 2019Updated 6 years ago
- Example project with Qt GUI controlling servo on Arduino UNO, over HDLC protocol.☆11Sep 29, 2015Updated 10 years ago
- 使用Cordic算法函数运算,在资源受限的设备上运行(如资源较少的FPGA、嵌入式MCU),避免了浮点运算、乘法、除法,只用移位和加法函数的计算。☆11Mar 22, 2024Updated last year
- Python utility to listen, timestamp and log data received from a serial port.☆11Aug 28, 2023Updated 2 years ago
- TACAN and ICLS beacon mod for DCS☆14Dec 14, 2025Updated 2 months ago
- This repository provides examples that demonstrates how to develop PSoC 4 MCU based analog designs. These examples help you to use periph…☆15Oct 27, 2018Updated 7 years ago
- This is a program that reads in vehicle dynamics data from CSV files and outputs them into useful charts to help analyze data.☆13Dec 18, 2023Updated 2 years ago
- A GUI to help users visualize the structure of a verilog HDL project☆12Jul 26, 2015Updated 10 years ago
- Schematics, footprints and scripts I've made and tested for KiCad☆11Jun 24, 2020Updated 5 years ago
- Support for automatic address map generation and address decoding logic for Wishbone connected hierachical systems☆12Feb 9, 2026Updated 3 weeks ago
- PWM Input measurement code for the Raspberry Pi Pico PIO☆10Apr 5, 2021Updated 4 years ago
- An Arduino library for the SH1106 LCD chipset☆11Jul 2, 2017Updated 8 years ago
- Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.☆11Jan 15, 2022Updated 4 years ago
- RF Module with STM8S103F3P6 and EV1527☆11Oct 29, 2016Updated 9 years ago
- a very very simple flash translation layer(FTL) algorithm☆12Feb 14, 2017Updated 9 years ago
- A public mirror of the private flight software development repository. Updated around every month or so☆12May 6, 2020Updated 5 years ago
- fasmg implementation of ARMv6-M instruction set☆12Apr 17, 2024Updated last year
- Plotting realtime data from XBee for Cansat competition☆12Jun 17, 2015Updated 10 years ago
- Implementation of Arinc standards including A429☆12Oct 12, 2016Updated 9 years ago
- ☆12Dec 28, 2022Updated 3 years ago
- UltraZed Edition examples☆12Oct 29, 2017Updated 8 years ago
- ☆13Feb 28, 2016Updated 10 years ago
- An attempt to model an a320 PFD display only with CSS, HTML, React, and some JS☆13Dec 19, 2017Updated 8 years ago
- BinView is a prototype for an application for binary data visualization. It can be used for analyzing large binary blocks and/or files, a…☆14Feb 16, 2015Updated 11 years ago
- Sources only, read-only mirror from hathach/tinyusb☆13Updated this week
- DSP University Project - Matlab, Simulations, and Verilog Files☆13Jan 14, 2020Updated 6 years ago