ptracton / UART_ECHO
Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.
☆13Updated 10 years ago
Alternatives and similar repositories for UART_ECHO
Users that are interested in UART_ECHO are comparing it to the libraries listed below
Sorting:
- SPI-Flash XIP Interface (Verilog)☆37Updated 3 years ago
- Testbenches for HDL projects☆16Updated this week
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆32Updated 5 years ago
- A Voila-Jones face detector hardware implementation☆32Updated 6 years ago
- 基于arm cortex-m0内核的xillinx fpga sopc工程项目☆12Updated 5 years ago
- FPGA Technology Exchange Group相关文件管理☆44Updated last month
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆26Updated 6 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆70Updated 2 years ago
- development interface mil-std-1553b for system on chip☆21Updated 7 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆49Updated 2 years ago
- 基于FPGA的PCIe 板卡,支持 离散量输入输出、ARINC429协议☆15Updated 2 years ago
- Simple mono FM Radio.☆48Updated 8 years ago
- turbo 8051☆29Updated 7 years ago
- RTL for mipi serialize and deserialize☆11Updated 7 years ago
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆28Updated 8 years ago
- Explanation of FPGA code for 8 PDM microphones in Matrix Creator☆12Updated 4 years ago
- QSPI for SoC☆22Updated 5 years ago
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆33Updated 7 years ago
- SEA-S7_gesture recognition☆15Updated 4 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board☆12Updated 6 years ago
- USB 1.1 PHY☆11Updated 10 years ago
- USB Full Speed PHY☆44Updated 5 years ago
- USB serial device (CDC-ACM)☆38Updated 4 years ago
- UART To SPI☆17Updated 10 years ago
- Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现☆24Updated last year
- USB1.1 Host Controller + PHY☆14Updated 3 years ago
- The CORDIC algorithm implemented in Octave/MATLAB and Verilog☆29Updated 10 years ago
- Reindeer Soft CPU for Step CYC10 FPGA board☆27Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago