GuzTech / vivado-picorv32

Related projects: ⓘ

• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆21Updated 9 months ago
• suoto / fpga_cores
  ☆32Updated last year
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆40Updated 2 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆40Updated 9 months ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆25Updated 6 months ago
• noasic / noasic
  An open-source VHDL library for FPGA design.
  ☆31Updated 2 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆28Updated this week
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆68Updated 2 years ago
• antmicro / cocotb-verilator-build
  ☆25Updated last year
• Xilinx / revCtrl
  Revision Control Labs and Materials
  ☆23Updated 6 years ago
• VHDL / news
  VHDL related news.
  ☆24Updated this week
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆34Updated 3 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆52Updated last year
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆14Updated 4 years ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆23Updated 4 months ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆22Updated last year
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆13Updated 5 months ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆52Updated 3 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆39Updated 6 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆39Updated 3 months ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆46Updated this week
• CESNET / sphinx-vhdl
  ☆20Updated last month
• VUnit / tdd-intro
  Example of Test Driven Design with VUnit
  ☆12Updated 2 years ago
• rftafas / stdcores
  Standard and Curated cores, tested and working.
  ☆11Updated last year
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 8 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆22Updated last week
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆28Updated 2 years ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆46Updated 6 months ago