risclite / ARM9-compatible-soft-CPU-core
This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lin…
☆72Updated 3 years ago
Related projects: ⓘ
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆77Updated 4 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆119Updated 5 years ago
- turbo 8051☆28Updated 7 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆69Updated 5 months ago
- Another tiny RISC-V implementation☆51Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆75Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆72Updated last year
- Converts ELF files to HEX files that are suitable for Verilog's readmemh.☆81Updated 2 years ago
- Verilog implementation of a RISC-V core☆101Updated 5 years ago
- Yet Another RISC-V Implementation☆82Updated 8 months ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆56Updated 6 years ago
- Basic RISC-V Test SoC☆102Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆57Updated 4 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆20Updated 4 years ago
- OpenXuantie - OpenE906 Core☆128Updated 2 months ago
- JTAG Test Access Port (TAP)☆30Updated 10 years ago
- ☆31Updated last year
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆161Updated 4 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆20Updated last year
- 8051 core☆92Updated 10 years ago
- I2C controller core☆30Updated last year
- RISCV model for Verilator/FPGA targets☆44Updated 4 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆66Updated 3 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆86Updated 3 years ago
- OpenXuantie - OpenE902 Core☆129Updated 2 months ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆196Updated 4 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆104Updated 4 years ago
- UART 16550 core☆29Updated 10 years ago
- TCP/IP controlled VPI JTAG Interface.☆58Updated 2 years ago
- WISHBONE SD Card Controller IP Core☆114Updated 2 years ago