This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lin…
☆95Oct 14, 2020Updated 6 years ago
Alternatives and similar repositories for ARM9-compatible-soft-CPU-core
Users that are interested in ARM9-compatible-soft-CPU-core are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 💎 A 32-bit ARM Processor Implementation in Verilog HDL☆31Mar 21, 2022Updated 4 years ago
- Verilog Implementation of an ARM LEGv8 CPU☆114Oct 3, 2018Updated 8 years ago
- Implemetation of pipelined ARM7TDMI processor in Verilog☆98Apr 19, 2018Updated 8 years ago
- 8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.☆209Oct 9, 2019Updated 7 years ago
- Amber ARM-compatible core☆18Jul 17, 2014Updated 12 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- a multiplier÷r verilog RTL file for RV32M instructions☆14Mar 17, 2020Updated 6 years ago
- ☆10Nov 8, 2019Updated 6 years ago
- SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.☆239Aug 25, 2020Updated 6 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 7 years ago
- personal practice☆11Sep 18, 2026Updated last month
- This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by …☆11May 11, 2023Updated 3 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆28Oct 8, 2018Updated 8 years ago
- Car Diagnostics Software compatible with ELM327 OBD usb device☆11May 10, 2025Updated last year
- ASIC Design of the openSPARC Floating Point Unit☆17Mar 13, 2017Updated 9 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- PowerPC implemented in Verilog for an FPGA.☆14Sep 12, 2024Updated 2 years ago
- Partial Verilog implimentation of a WiMAX OFDM Phy☆19May 28, 2012Updated 14 years ago
- RISC OS Filecore Tools for Linux☆12Apr 10, 2026Updated 6 months ago
- Image viewer and editor for RISC OS, plus the AppEngine desktop C library☆13Oct 24, 2026Updated last week
- 基于arm cortex-m0内核的xillinx fpga sopc工程项目☆13May 28, 2019Updated 7 years ago
- Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System…☆13Oct 8, 2017Updated 9 years ago
- DMA controller for CNN accelerator☆15May 22, 2017Updated 9 years ago
- OpenSPARC-based SoC☆78Jul 17, 2014Updated 12 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- 正点原子开拓者&新起点FPGA开发板例程☆16Nov 29, 2019Updated 6 years ago
- Mirror of git://git.zerfleddert.de/usb-driver☆22Aug 9, 2013Updated 13 years ago
- Hardware implementation of HDR image producing algorithm☆16Sep 30, 2022Updated 4 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 7 months ago
- ☆26Oct 31, 2020Updated 6 years ago
- View Acorn/RISC OS Draw, Vector or Poster files on any Linux or Unix system☆10May 10, 2025Updated last year
- ARM-CPU implemented verilog☆30Jan 13, 2024Updated 2 years ago
- 给定ARM Cortex-M3的软核，扩展周围的AMBA总线以及基本外设，完成在上面的汇编以及C语言的执行☆19Aug 26, 2019Updated 7 years ago
- ☆15Sep 23, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- An open-source, cross-platform application for Acorn ADFS and DFS disc image manipulation☆14Apr 10, 2018Updated 8 years ago
- Pipelined 64-bit RISC-V core☆17Mar 7, 2024Updated 2 years ago
- a super-simple pipelined verilog divider. flexible to define stages☆61Jul 25, 2019Updated 7 years ago
- ☆14Oct 19, 2019Updated 7 years ago
- commit rtl and build cosim env☆16Feb 15, 2024Updated 2 years ago
- !UCDebug, ARM debugger for RISC OS☆13Dec 23, 2021Updated 4 years ago
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆128Aug 28, 2019Updated 7 years ago