Alternatives and similar repositories for flower_classification_vai_tf_numpy_array:

Users that are interested in flower_classification_vai_tf_numpy_array are comparing it to the libraries listed below

• HWAC-DL / hwac_object_tracker
  FPGA accelerated TinyYOLO v2 object detection neural network
  ☆71Updated 6 years ago
• markcxli / FPGA_DPU
  This project is to implement YOLO v3 on Xilinx FPGA with DPU
  ☆54Updated 5 years ago
• gewuek / vitis_ai_custom_platform_flow
  This project is trying to create a base vitis platform to run with DPU
  ☆46Updated 4 years ago
• JinChen-tw / pynqz2_dpu140
  This TRD is implement DPU v1.4.0 on PYNQ-Z2 board
  ☆44Updated 4 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆46Updated 7 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆27Updated 5 years ago
• sumilao / Zynq-7000-DPU-TRD
  Zynq-7000 DPU TRD
  ☆44Updated 5 years ago
• wutianze / dnndk-pynqz2
  First lesson for you to use DNNDK, also it can be helpful for your AI learning
  ☆68Updated last year
• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆107Updated 5 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆54Updated 10 years ago
• yztong / LeNet_RTL
  An LeNet RTL implement onto FPGA
  ☆45Updated 6 years ago
• xupsh / Pynq-CV-OV5640
  Pynq computer vision examples with an OV5640 camera
  ☆46Updated 5 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆64Updated 6 years ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆47Updated 5 years ago
• ilaydayaman / CNN_for_SLR
  A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
  ☆94Updated last year
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆71Updated last year
• mfarhadi / CNNIOT
  ☆45Updated 6 years ago
• drichmond / PYNQ-HLS
  A Tutorial on Putting High-Level Synthesis cores in PYNQ
  ☆104Updated 6 years ago
• zhan6841 / FPGA-Accelerator-for-AES-LeNet-VGG16
  FPGA/AES/LeNet/VGG16
  ☆102Updated 6 years ago
• Pieter-Berteloot / PYNQ_Projects
  Pynq projects and guides
  ☆27Updated 6 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆61Updated 8 months ago
• yportne13 / SpinalResNet
  AdderNet ResNet20 for cifar10 written in SpinalHDL
  ☆32Updated 4 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆36Updated 8 years ago
• canteen-man / CNN_FPGA_ZYNQ_PYNQ
  hls code zynq 7020 pynq z2 CNN
  ☆84Updated 6 years ago
• xupsh / 2019_SummerCamp
  2019 SEU-Xilinx Summer School
  ☆49Updated 5 years ago
• djtfoo / lenet5-verilog
  A Verilog design of LeNet-5, a Convolutional Neural Network architecture
  ☆28Updated 4 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆48Updated 2 years ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆216Updated last year
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆50Updated 7 years ago
• xupgit / Advanced-Embedded-System-Design-Flow-on-Zynq
  ☆51Updated 5 years ago