xkw168 / Digital-recognitionLinks
digital recognition base on FPGA
☆13Updated 5 years ago
Alternatives and similar repositories for Digital-recognition
Users that are interested in Digital-recognition are comparing it to the libraries listed below
Sorting:
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- ☆36Updated 9 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- ☆68Updated 9 years ago
- AXI Interconnect☆51Updated 3 years ago
- Generic AXI to AHB bridge☆17Updated 11 years ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆21Updated 3 years ago
- ☆10Updated 5 years ago
- 异步FIFO的内部实现☆24Updated 6 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- FFT implement by verilog_测试验证已通过☆58Updated 8 years ago
- Implementation of the PCIe physical layer☆47Updated 3 weeks ago
- ☆26Updated 4 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- verilog☆21Updated 2 years ago
- upgrade to e203 (a risc-v core)☆44Updated 5 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆14Updated 3 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- Cortex M0 based SoC☆74Updated 3 years ago
- AXI总线连接器☆103Updated 5 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 11 years ago
- 视频旋转(2019FPGA大赛)☆35Updated 5 years ago
- ☆72Updated 4 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆48Updated 5 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆23Updated 5 years ago