xkw168 / Digital-recognitionLinks
digital recognition base on FPGA
☆12Updated 6 years ago
Alternatives and similar repositories for Digital-recognition
Users that are interested in Digital-recognition are comparing it to the libraries listed below
Sorting:
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago
- ☆38Updated 10 years ago
- AXI Interconnect☆54Updated 4 years ago
- 异步FIFO的内部实现☆25Updated 7 years ago
- 基于FPGA的图像处理模块(出 自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆50Updated 5 years ago
- ☆11Updated 5 years ago
- verilog☆21Updated 2 years ago
- Implementation of the PCIe physical layer☆60Updated 5 months ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- ☆75Updated 4 years ago
- ☆26Updated 4 years ago
- AHB DMA 32 / 64 bits☆57Updated 11 years ago
- SPI interface connect to APB BUS with Verilog HDL☆39Updated 4 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆15Updated 3 years ago
- 视频旋转(2019FPGA大赛)☆37Updated 5 years ago
- ☆28Updated 5 months ago
- ☆73Updated 9 years ago
- Build an open source, extremely simple DMA.☆23Updated 6 years ago
- AXI总线连接器☆105Updated 5 years ago
- ahb scram controller, design and verification☆27Updated 7 years ago
- PCIE 5.0 Graduation project (Verification Team)☆96Updated last year
- 支持AXI总线协议的8k×8 SP SRAM☆26Updated 5 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 6 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆22Updated 4 years ago
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆17Updated 5 years ago