xkw168 / Digital-recognitionLinks
digital recognition base on FPGA
☆13Updated 5 years ago
Alternatives and similar repositories for Digital-recognition
Users that are interested in Digital-recognition are comparing it to the libraries listed below
Sorting:
- 学习AXI接口,以及xilinx DDR3 IP使用☆37Updated 8 years ago
- ☆36Updated 9 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆42Updated 3 years ago
- ☆25Updated 4 years ago
- FFT implement by verilog_测试验证已通过☆58Updated 8 years ago
- AXI Interconnect☆50Updated 3 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆48Updated 5 years ago
- verilog☆21Updated 2 years ago
- ☆10Updated 5 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- ☆56Updated 2 years ago
- 异步FIFO的内部实现☆24Updated 6 years ago
- upgrade to e203 (a risc-v core)☆44Updated 4 years ago
- Build an open source, extremely simple DMA.☆22Updated 6 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆14Updated 3 years ago
- Must-have verilog systemverilog modules☆36Updated 3 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- ☆67Updated 9 years ago
- AXI总线连接器☆100Updated 5 years ago
- SPI interface connect to APB BUS with Verilog HDL☆34Updated 4 years ago
- ☆23Updated 5 years ago
- 2018第二届全国大学生FPGA创新设计邀请赛的作品☆60Updated 6 years ago
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- AHB Bus lite v3.0☆16Updated 5 years ago
- Implementation of the PCIe physical layer☆45Updated this week
- ARM中通过APB总线连接的UART模块☆67Updated 5 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆17Updated 10 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆54Updated 7 years ago