Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
☆57Sep 15, 2020Updated 5 years ago
Alternatives and similar repositories for rigel
Users that are interested in rigel are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Darkroom Core☆48Oct 7, 2017Updated 8 years ago
- A Vivado HLS Command Line Helper Tool☆36Oct 6, 2021Updated 4 years ago
- Fork of Hipacc generating code for Vivado HLS and Altera OpenCL☆24Oct 8, 2018Updated 7 years ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Sep 13, 2023Updated 2 years ago
- Peak : Processor Specification Language ala Newell and Bell's ISP☆21Dec 5, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Mar 29, 2021Updated 5 years ago
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated 3 months ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- Fast PnR toolchain for CGRA☆18Jul 26, 2024Updated last year
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago
- ☆11Sep 14, 2020Updated 5 years ago
- Pono: A flexible and extensible SMT-based model checker☆123May 7, 2026Updated 2 weeks ago
- Another dynamically-typed, lightweight programming language☆12May 5, 2015Updated 11 years ago
- Github for CS448H Winter 2017☆14Jun 26, 2018Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆98Jan 29, 2026Updated 3 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Feb 17, 2021Updated 5 years ago
- ☆105Jun 27, 2022Updated 3 years ago
- RISCV Core written in Calyx☆17Aug 16, 2024Updated last year
- Scala staging framework☆18Jul 13, 2018Updated 7 years ago
- Time-sensitive affine types for predictable hardware generation☆152Jan 5, 2026Updated 4 months ago
- A domain-specific language and compiler for image processing☆78Mar 20, 2021Updated 5 years ago
- Base code and optimized code for the benchmarks used in the PolyMage paper published at ASPLOS 2015☆20Jun 14, 2016Updated 9 years ago
- Verilog AST☆21Dec 2, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- magma circuits☆265Oct 19, 2024Updated last year
- An open source high level synthesis (HLS) tool built on top of LLVM☆130Jun 11, 2024Updated last year
- ☆30Oct 16, 2022Updated 3 years ago
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 4 years ago
- HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration☆15Sep 14, 2020Updated 5 years ago
- STLC-related snippets in Agda☆16May 1, 2013Updated 13 years ago
- DASS HLS Compiler☆31Oct 4, 2023Updated 2 years ago
- Next generation CGRA generator☆120Updated this week
- A set of tools for building graph rewriting systems and more specifically, working with the chemlambda rewrite model of computation.☆12Dec 27, 2016Updated 9 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Tool for optimize CNN blocking☆95Mar 22, 2020Updated 6 years ago
- RTL implementation of a ray-tracing GPU☆16Dec 18, 2012Updated 13 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆46Apr 2, 2025Updated last year
- APL-like functions for use from Lua.☆18Mar 23, 2015Updated 11 years ago
- Lua/Terra + Java Native Interface☆21Mar 3, 2017Updated 9 years ago
- Public Release of Stream-Dataflow☆14May 17, 2019Updated 7 years ago
- A Just-In-Time Compiler for Verilog from VMware Research☆447Jul 1, 2021Updated 4 years ago