jameshegarty / rigel
Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
☆56Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for rigel
- The Shang high-level synthesis framework☆119Updated 10 years ago
- ☆101Updated 2 years ago
- Linear algebra accelerators for RISC-V (published in ICCD 17)☆66Updated 7 years ago
- firrtlator is a FIRRTL C++ library☆21Updated 7 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 3 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆97Updated 4 years ago
- CoreIR Symbolic Analyzer☆61Updated 4 years ago
- ☆25Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 2 years ago
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆15Updated 5 years ago
- A Verilog Synthesis Regression Test☆34Updated 7 months ago
- netlistDB - Intermediate format for digital hardware representation with graph database API☆29Updated 3 years ago
- Riscy Processors - Open-Sourced RISC-V Processors☆72Updated 5 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated last year
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆12Updated 3 years ago
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 8 years ago
- Bluespec BSV HLHDL tutorial☆92Updated 8 years ago
- Peak : Processor Specification Language ala Newell and Bell's ISP☆19Updated 11 months ago
- Next generation CGRA generator☆106Updated this week
- Z-scale Microarchitectural Implementation of RV32 ISA☆54Updated 7 years ago
- Exploration of alternative hardware description languages☆28Updated 6 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆18Updated this week
- An advanced header-only exact synthesis library☆23Updated last year
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆37Updated 8 years ago
- An executable specification of the RISCV ISA in L3.☆41Updated 5 years ago
- The PE for the second generation CGRA (garnet).☆16Updated 2 months ago
- Floating point modules for CHISEL☆28Updated 10 years ago
- A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)☆20Updated 7 years ago