Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
☆57Sep 15, 2020Updated 5 years ago
Alternatives and similar repositories for rigel
Users that are interested in rigel are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Darkroom Core☆48Oct 7, 2017Updated 8 years ago
- A Vivado HLS Command Line Helper Tool☆36Oct 6, 2021Updated 4 years ago
- Fork of Hipacc generating code for Vivado HLS and Altera OpenCL☆24Oct 8, 2018Updated 7 years ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Sep 13, 2023Updated 2 years ago
- Peak : Processor Specification Language ala Newell and Bell's ISP☆21Dec 5, 2023Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Mar 29, 2021Updated 5 years ago
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated 4 months ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- Python bindings for coreir☆11Sep 13, 2023Updated 2 years ago
- HLS branch of Halide☆78Jul 6, 2018Updated 7 years ago
- Fast PnR toolchain for CGRA☆18Jul 26, 2024Updated last year
- Integration test for entire CGRA flow☆12Jan 17, 2020Updated 6 years ago
- ☆11Sep 14, 2020Updated 5 years ago
- Pono: A flexible and extensible SMT-based model checker☆125Jun 4, 2026Updated last month
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Another dynamically-typed, lightweight programming language☆12May 5, 2015Updated 11 years ago
- Github for CS448H Winter 2017☆14Jun 26, 2018Updated 8 years ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Feb 17, 2021Updated 5 years ago
- Time-sensitive affine types for predictable hardware generation☆152Jan 5, 2026Updated 5 months ago
- Verilog AST☆21Dec 2, 2023Updated 2 years ago
- magma circuits☆263Oct 19, 2024Updated last year
- An open source high level synthesis (HLS) tool built on top of LLVM☆130Jun 11, 2024Updated 2 years ago
- ☆30Oct 16, 2022Updated 3 years ago
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A polyhedral compiler for hardware accelerators☆59Jul 24, 2024Updated last year
- Stencil with Optimized Dataflow Architecture☆18Feb 27, 2024Updated 2 years ago
- DASS HLS Compiler☆31Oct 4, 2023Updated 2 years ago
- Next generation CGRA generator☆119May 26, 2026Updated last month
- The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom boa…☆20Jul 9, 2024Updated last year
- A set of tools for building graph rewriting systems and more specifically, working with the chemlambda rewrite model of computation.☆12Dec 27, 2016Updated 9 years ago
- Tool for optimize CNN blocking☆95Mar 22, 2020Updated 6 years ago
- ☆40Sep 17, 2021Updated 4 years ago
- RTL implementation of a ray-tracing GPU☆16Dec 18, 2012Updated 13 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆87Mar 5, 2024Updated 2 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆46Apr 2, 2025Updated last year
- APL-like functions for use from Lua.☆18Mar 23, 2015Updated 11 years ago
- Public Release of Stream-Dataflow☆14May 17, 2019Updated 7 years ago
- A Just-In-Time Compiler for Verilog from VMware Research☆446Jul 1, 2021Updated 5 years ago
- RedEye is a vision sensor designed to execute early stages of a deep convolutional neural network (ConvNet) in the analog domain. This re…☆14Dec 16, 2016Updated 9 years ago
- A heuristic procedure for proving inequalities☆36Sep 4, 2018Updated 7 years ago