PacktPublishing / Architecting-and-Building-High-Speed-SoCsLinks
Architecting and Building High Speed SoCs, published by Packt
☆29Updated 2 years ago
Alternatives and similar repositories for Architecting-and-Building-High-Speed-SoCs
Users that are interested in Architecting-and-Building-High-Speed-SoCs are comparing it to the libraries listed below
Sorting:
- A reference book on System-on-Chip Design☆36Updated 4 months ago
 - The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆36Updated 2 years ago
 - Open source ISS and logic RISC-V 32 bit project☆61Updated 2 weeks ago
 - A textbook on understanding system on chip design☆48Updated 4 months ago
 - PQR5ASM is a RISC-V Assembler compliant with RV32I☆19Updated 6 months ago
 - Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆65Updated 11 months ago
 - Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos Schoo…☆50Updated 3 years ago
 - ☆40Updated last year
 - 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆27Updated 2 weeks ago
 - A place to keep my synthesizable verilog examples.☆47Updated 6 months ago
 - 256-bit vector processor based on the RISC-V vector (V) extension☆30Updated 4 years ago
 - ☆47Updated 2 years ago
 - Proposed RISC-V Composable Custom Extensions Specification☆70Updated 4 months ago
 - The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆121Updated 3 months ago
 - Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 8 months ago
 - RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆20Updated 2 years ago
 - Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt☆104Updated 6 months ago
 - Raptor end-to-end FPGA Compiler and GUI☆86Updated 10 months ago
 - An implementation of RISC-V☆43Updated last month
 - RTL data structure☆52Updated 2 months ago
 - RISC-V Nox core☆68Updated 3 months ago
 - ☆80Updated last week
 - Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆26Updated last year
 - Flip flop setup, hold & metastability explorer tool☆51Updated 3 years ago
 - Simple runtime for Pulp platforms☆49Updated last month
 - Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆112Updated 2 years ago
 - Open Source PHY v2☆31Updated last year
 - Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆67Updated last month
 - The multi-core cluster of a PULP system.☆109Updated this week
 - Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process☆18Updated 7 months ago