Alternatives and similar repositories for Architecting-and-Building-High-Speed-SoCs

Users that are interested in Architecting-and-Building-High-Speed-SoCs are comparing it to the libraries listed below

• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆61Updated 3 weeks ago
• arm-university / System-on-Chip-Design-with-Arm-Cortex-M-Processors
  A reference book on System-on-Chip Design
  ☆37Updated 6 months ago
• Weiyet / RTLStructLib
  RTL data structure
  ☆59Updated this week
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• arm-university / Fundamentals-of-System-on-Chip-Design-on-Arm-Cortex-M-Microcontrollers
  A textbook on understanding system on chip design
  ☆58Updated 6 months ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆65Updated last year
• PacktPublishing / Architecting-High-Performance-Embedded-Systems
  ☆70Updated 2 years ago
• iammituraj / pqr5asm
  PQR5ASM is a RISC-V Assembler compliant with RV32I
  ☆19Updated 8 months ago
• fpgaemu / fpgaemu
  Introduction to FPGA emulation and digital design. This capstone project was part of the 2021 University of San Diego Shiley-Marcos Schoo…
  ☆53Updated 3 years ago
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆118Updated 3 months ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated last month
• Xilinx / xup_fpga_vivado_flow
  AMD Xilinx University Program Vivado tutorial
  ☆43Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆124Updated 5 months ago
• PacktPublishing / Learn-FPGA-Programming
  Learn FPGA Programming, published by Packt
  ☆202Updated last year
• fpgadeveloper / ethernet-fmc-processorless
  Example designs for using Ethernet FMC without a processor (ie. state machine based)
  ☆34Updated last year
• ATaylorCEngFIET / Mastering_AMD_MicroBlaze_Processor_The_PetaLinux_Class
  ☆17Updated last year
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆21Updated 2 years ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆31Updated 4 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆68Updated 10 months ago
• rivosinc / hammer
  Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.
  ☆39Updated 4 months ago
• ATaylorCEngFIET / Professional-PYNQ
  ☆14Updated 2 years ago
• IBM / hdl-tools
  Facilitates building open source tools for working with hardware description languages (HDLs)
  ☆66Updated 6 years ago
• HDLForBeginners / Examples
  ☆115Updated 2 years ago
• aignacio / nox
  RISC-V Nox core
  ☆71Updated 5 months ago
• wyvernSemi / vproc
  Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
  ☆69Updated 3 months ago
• os-fpga / Raptor
  Raptor end-to-end FPGA Compiler and GUI
  ☆93Updated last year
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆63Updated last month
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆31Updated last year
• kiwih / qtcore-C1
  ☆47Updated 2 years ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 6 months ago