Alternatives and similar repositories for Architecting-and-Building-High-Speed-SoCs

Users that are interested in Architecting-and-Building-High-Speed-SoCs are comparing it to the libraries listed below

• iammituraj / pqr5asm
  PQR5ASM is a RISC-V Assembler compliant with RV32I
  ☆19Updated 2 months ago
• arm-university / System-on-Chip-Design-with-Arm-Cortex-M-Processors
  A reference book on System-on-Chip Design
  ☆29Updated last week
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆54Updated 2 weeks ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆59Updated 7 months ago
• PacktPublishing / Architecting-High-Performance-Embedded-Systems
  ☆68Updated 2 years ago
• efard / DSPHDL
  Digital Signal Processing and Well-Known Modulations on HDL
  ☆41Updated last month
• ATaylorCEngFIET / Professional-PYNQ
  ☆14Updated last year
• TinyTapeout / tinytapeout-ihp-0p1
  Experimental Tiny Tapeout chip on IHP SG13G2 0.13 μm BiCMOS process
  ☆18Updated 2 months ago
• antmicro / renode-verilator-integration
  This repository contains sample code integrating Renode with Verilator
  ☆19Updated last month
• PacktPublishing / The-FPGA-Programming-Handbook-Second-Edition
  Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt
  ☆91Updated 2 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆66Updated 4 months ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆19Updated 2 years ago
• adonairc / tt07-dda-van-der-pol
  DDA solver for the van der Pol oscillator using 16-bit posits
  ☆28Updated 5 months ago
• ATaylorCEngFIET / Mastering_AMD_MicroBlaze_Processor_The_PetaLinux_Class
  ☆17Updated last year
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• merldsu / SAP_FPU
  This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.
  ☆18Updated 2 years ago
• HDLForBeginners / Examples
  ☆94Updated last year
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆35Updated 4 years ago
• kmkalpana2001 / DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
  ☆41Updated last year
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆46Updated last year
• ATaylorCEngFIET / Getting-to-Know-Vivado
  Source files for Getting to Know Vivado course
  ☆19Updated 4 years ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆42Updated 4 months ago
• Xilinx / xup_fpga_vivado_flow
  AMD Xilinx University Program Vivado tutorial
  ☆41Updated 2 years ago
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆55Updated last year
• MicrochipTech / fpga-hls-examples
  Open-Source HLS Examples for Microchip FPGAs
  ☆45Updated last week
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆35Updated 2 years ago
• fpgadeveloper / ethernet-fmc-processorless
  Example designs for using Ethernet FMC without a processor (ie. state machine based)
  ☆31Updated 7 months ago
• ATaylorCEngFIET / introduction_to_vivado
  ☆20Updated 2 years ago
• Weiyet / RTLStructLib
  RTL data structure
  ☆51Updated this week
• ATaylorCEngFIET / Vitis_Hero
  ☆28Updated 3 years ago