IHP 130nm ASIC tapeout of a 2x2 bfloat16 matrix matrix multiplication with DFT infrastructure. Iteration on the previous accelerator taped out on GF180.
☆42Jul 10, 2026Updated last month
Alternatives and similar repositories for Systolic_Array_with_DFT_v2
Users that are interested in Systolic_Array_with_DFT_v2 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RTL implementation of a performance/area optimized bfloat16 adder and multiplication.☆34Mar 28, 2026Updated 4 months ago
- SKY130A implementatoin of the Blake2s hash algorithm☆26Dec 3, 2025Updated 8 months ago
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 6 months ago
- GF180 ASIC tapeout of a 2x2 MAC with DFT infrastructure☆71Aug 12, 2026Updated last week
- Convert an image to a GDS format for inclusion in a zerotoasic project☆19Jun 16, 2022Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Testfield: T593☆15Apr 27, 2026Updated 3 months ago
- ElemRV - End-to-end Open-Source RISC-V Microcontroller☆141Updated this week
- The first-ever opensource soft core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers. With sta…☆81Jul 11, 2026Updated last month
- ☆39Jul 23, 2026Updated last month
- A library of open PDK packages☆127Aug 19, 2026Updated last week
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆122Jun 18, 2026Updated 2 months ago
- An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled t…☆23Jun 14, 2026Updated 2 months ago
- A template-based, layer-oriented High Level Synthesis Tool for AI algorithms☆15Jul 20, 2026Updated last month
- List of several designs I have been working through the years to avoid re-designing it again☆16Jun 17, 2024Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a log…☆76Feb 12, 2026Updated 6 months ago
- An Open-Source Full-Custom Silicon Compiler for High-Performance FPGA Fabrics☆18Aug 14, 2026Updated last week
- Cloneless1 is an open-source tamper-resistant cryptographic ASIC design☆24Jul 30, 2026Updated 3 weeks ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆25Nov 9, 2025Updated 9 months ago
- 32-Bit RISC microprocessor system for FPGA boards☆37Nov 29, 2024Updated last year
- This project contains Verilog designs and a PCB for the implementation of CSI-2 camera interface to HDMI bridge on a Gatemate FPGA from C…☆21Jul 28, 2025Updated last year
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆266Updated this week
- Source code & scripts for experimental characterization and demonstration of 1) simultaneous many-row activation, 2) up to nine-input maj…☆18May 17, 2024Updated 2 years ago
- PCIe GEN1, GEN2 and GEN3 Scrambler, This Scrambler is able to scramble 1,2 and 4 bytes of data in 1 clock cycle in respect to the scrambl…☆18Jul 19, 2026Updated last month
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).☆23Jul 23, 2026Updated last month
- ☆26Updated this week
- A simple spidergon network-on-chip with wormhole switching feature☆13Mar 22, 2021Updated 5 years ago
- RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.☆113Dec 24, 2023Updated 2 years ago
- 3.3V SRAM macros for GF180MCU, based on the original 5V SRAM macros.☆23Jun 19, 2026Updated 2 months ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12May 6, 2019Updated 7 years ago
- ☆156Aug 19, 2026Updated last week
- 32-bit 5-stage pipelined RISC-V processor in SystemVerilog☆40Oct 29, 2023Updated 2 years ago
- Advanced Integrated Circuits 2025☆14Nov 1, 2025Updated 9 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆72Apr 13, 2024Updated 2 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21Updated this week
- HeiChips 2025 LibreLane Workshop☆17Aug 25, 2025Updated last year
- Generate symbols from HDL components/modules☆22Feb 6, 2023Updated 3 years ago
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 3 years ago
- LEVEL: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framew…☆31Jul 6, 2026Updated last month
- ☆15Feb 18, 2025Updated last year