OVGN / OpenHBMC
Open-source high performance AXI4-based HyperRAM memory controller
☆69Updated 2 years ago
Alternatives and similar repositories for OpenHBMC:
Users that are interested in OpenHBMC are comparing it to the libraries listed below
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆66Updated 2 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- SDRAM controller with AXI4 interface☆89Updated 5 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆76Updated 11 months ago
- ☆25Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆101Updated 3 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 3 months ago
- RISCV model for Verilator/FPGA targets☆50Updated 5 years ago
- USB 2.0 Device IP Core☆63Updated 7 years ago
- RTL Verilog library for various DSP modules☆85Updated 3 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆122Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- SPI-Flash XIP Interface (Verilog)☆36Updated 3 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated 11 months ago
- Verilog digital signal processing components☆129Updated 2 years ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆93Updated 4 years ago
- TCP/IP controlled VPI JTAG Interface.☆65Updated 2 months ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆42Updated 10 months ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆16Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- I2C controller core☆39Updated 2 years ago
- open-source Ethenet media access controller for Ariane on Genesys-2☆18Updated 5 years ago
- Repository gathering basic modules for CDC purpose☆53Updated 5 years ago
- DDR2 memory controller written in Verilog☆74Updated 13 years ago
- ☆56Updated 2 years ago