Open-source high performance AXI4-based HyperRAM memory controller
☆84Oct 6, 2022Updated 3 years ago
Alternatives and similar repositories for OpenHBMC
Users that are interested in OpenHBMC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Portable HyperRAM controller☆65Dec 8, 2024Updated last year
- ☆36Dec 22, 2025Updated 3 months ago
- SDRAM controller with AXI4 interface☆103Aug 8, 2019Updated 6 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆64Jan 8, 2019Updated 7 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆92Aug 10, 2018Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- File editor for the Xilinx AXI Traffic Generator IP☆17Feb 9, 2026Updated 2 months ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 6 years ago
- Python script for generating Xilinx .coe files for RAM initializing☆18Jan 3, 2019Updated 7 years ago
- Open-source thermal camera project☆59Jul 28, 2022Updated 3 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- SPI ELF bootloader for Xilinx Microblaze processors☆27Oct 17, 2017Updated 8 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆24Nov 7, 2018Updated 7 years ago
- UART -> AXI Bridge☆72Jul 1, 2021Updated 4 years ago
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆11Dec 20, 2013Updated 12 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆72Dec 17, 2025Updated 3 months ago
- A simple, scalable, source-synchronous, all-digital DDR link☆37Apr 1, 2026Updated last week
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Implementation of a RISC-V CPU in Verilog.☆17Mar 2, 2025Updated last year
- ☆78Feb 4, 2021Updated 5 years ago
- Example Projects for the Microsemi SmartFusion 2☆11Dec 10, 2017Updated 8 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆27Mar 13, 2025Updated last year
- A small ANSI C static library to control terminals compatible with ANSI/ISO/VT-100 control sequences.☆18May 5, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Mar 6, 2018Updated 8 years ago
- A DDR3 memory controller in Verilog for various FPGAs☆582Oct 10, 2021Updated 4 years ago
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 4 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Aug 22, 2021Updated 4 years ago
- SPI master and SPI slave for FPGA written in VHDL☆181Apr 24, 2021Updated 4 years ago
- ☆12Jul 20, 2022Updated 3 years ago
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated 10 months ago
- Groundhog - Serial ATA Host Bus Adapter☆23Jun 10, 2018Updated 7 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆30Dec 1, 2016Updated 9 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43May 22, 2020Updated 5 years ago
- RISC-V processor☆32May 26, 2022Updated 3 years ago
- GameBoy Advance Zedboard Implementation☆18Dec 27, 2016Updated 9 years ago
- ☆17Jul 12, 2020Updated 5 years ago
- TCP/IP and UDP/IP protocol stack off-loading☆19Aug 9, 2020Updated 5 years ago
- ☆37Jan 11, 2021Updated 5 years ago