OVGN / OpenHBMCLinks
Open-source high performance AXI4-based HyperRAM memory controller
☆80Updated 3 years ago
Alternatives and similar repositories for OpenHBMC
Users that are interested in OpenHBMC are comparing it to the libraries listed below
Sorting:
- UART -> AXI Bridge☆68Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆93Updated 3 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆77Updated 3 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆52Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆68Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- Verilog wishbone components☆124Updated last year
- ☆33Updated this week
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆42Updated 3 months ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆83Updated last year
- ☆28Updated 4 years ago
- Verilog digital signal processing components☆162Updated 3 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆30Updated 2 years ago
- TCP/IP controlled VPI JTAG Interface.☆69Updated 11 months ago
- SPI-Flash XIP Interface (Verilog)☆48Updated 4 years ago
- USB 2.0 Device IP Core☆72Updated 8 years ago
- Verilog SPI master and slave☆62Updated 9 years ago
- FTDI FT600 SuperSpeed USB3.0 to AXI bus master☆96Updated 5 years ago
- Small (Q)SPI flash memory programmer in Verilog☆67Updated 3 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆72Updated 7 months ago
- RTL Verilog library for various DSP modules☆93Updated 3 years ago
- MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.☆132Updated 5 years ago
- FuseSoC standard core library☆150Updated 2 weeks ago
- ☆76Updated 3 years ago
- Antmicro's fast, vendor-neutral DMA IP in Chisel☆128Updated 7 months ago
- Wishbone interconnect utilities☆43Updated last week
- I2C controller core☆47Updated 2 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆159Updated 9 months ago