adki / Deep_Learning_BlocksLinks
DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep learning inference network.
☆23Updated 5 months ago
Alternatives and similar repositories for Deep_Learning_Blocks
Users that are interested in Deep_Learning_Blocks are comparing it to the libraries listed below
Sorting:
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- Implementing Different Adder Structures in Verilog☆74Updated 6 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆76Updated 5 years ago
- ☆47Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- DMA Hardware Description with Verilog☆19Updated 6 years ago
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆13Updated 3 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆39Updated 3 years ago
- Design and UVM-TB of RISC -V Microprocessor☆33Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Updated 2 years ago
- Verilog RTL Design☆46Updated 4 years ago
- BlackParrot on Zynq☆48Updated this week
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated last week
- Engineering Program on RTL Design for FPGA Accelerator☆33Updated 5 years ago
- ☆40Updated 6 years ago
- How to Accelerate an Image Upscaling CNN on FPGA Using HLS☆25Updated 4 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆26Updated 3 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆38Updated 3 years ago
- ☆63Updated last year
- This is the repository for the IEEE version of the book☆78Updated 5 years ago
- A 2D convolution hardware implementation written in Verilog☆51Updated 5 years ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆17Updated 3 years ago
- RTL Design and Verification☆17Updated 5 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆76Updated 6 years ago