adki / Deep_Learning_BlocksLinks
DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep learning inference network.
☆23Updated 5 months ago
Alternatives and similar repositories for Deep_Learning_Blocks
Users that are interested in Deep_Learning_Blocks are comparing it to the libraries listed below
Sorting:
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated 2 years ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- General Purpose AXI Direct Memory Access☆62Updated last year
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆76Updated 5 years ago
- BlackParrot on Zynq☆48Updated this week
- Design and UVM-TB of RISC -V Microprocessor☆33Updated last year
- Implementing Different Adder Structures in Verilog☆75Updated 6 years ago
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆74Updated last year
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆86Updated 2 years ago
- Verilog RTL Design☆46Updated 4 years ago
- ☆47Updated last year
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆39Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- This is the repository for the IEEE version of the book☆78Updated 5 years ago
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆13Updated 3 years ago
- ☆40Updated 6 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Updated this week
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆62Updated last month
- RTL Design and Verification☆17Updated 5 years ago
- ☆68Updated 3 years ago
- AMD Xilinx University Program Vivado tutorial☆43Updated 2 years ago
- RTL Verilog library for various DSP modules☆94Updated 3 years ago
- ☆54Updated 6 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆33Updated 4 years ago
- ☆82Updated 11 years ago
- ☆31Updated 5 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Updated 6 years ago