Alternatives and similar repositories for Deep_Learning_Blocks

Users that are interested in Deep_Learning_Blocks are comparing it to the libraries listed below

• merldsu / SAP_FPU
  This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.
  ☆18Updated 2 years ago
• adki / RTL-Design-For-FPGA
  Engineering Program on RTL Design for FPGA Accelerator
  ☆29Updated 4 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆32Updated 3 months ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆30Updated last week
• pulp-platform / apb
  APB Logic
  ☆18Updated 5 months ago
• obilaniu / MVU
  Neural Network accelerator powered by MVUs and RISC-V.
  ☆13Updated 9 months ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 6 months ago
• pulp-platform / rbe
  Reconfigurable Binary Engine
  ☆16Updated 4 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 5 years ago
• AmrElsersy / DMA
  DMA Hardware Description with Verilog
  ☆14Updated 5 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆32Updated last year
• dpretet / bster
  Implementation of a binary search tree algorithm in a FPGA/ASIC IP
  ☆19Updated 3 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆38Updated 3 years ago
• mnasser431998 / bfu_dif_fft_rtl
  The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor
  ☆14Updated 2 years ago
• MicrochipTech / fpga-hls-examples
  Open-Source HLS Examples for Microchip FPGAs
  ☆44Updated this week
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆54Updated 2 years ago
• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆25Updated this week
• yigitbektasgursoy / SDRAM_Verilog
  Verilog HDL implementation of SDRAM controller and SDRAM model
  ☆26Updated 10 months ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆54Updated 4 months ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆30Updated 3 years ago
• martinriis / RISC-V-Vector-Processor
  256-bit vector processor based on the RISC-V vector (V) extension
  ☆29Updated 4 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆15Updated 3 months ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆18Updated 2 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆37Updated 2 years ago
• arm-university / System-on-Chip-Design-with-Arm-Cortex-M-Processors
  A reference book on System-on-Chip Design
  ☆27Updated last year
• TheMozg / spi-amba-simulation
  ITMO SystemC & Verilog assignments - AMBA AHB and SPI
  ☆21Updated 7 years ago
• pulp-platform / axi_spi_slave
  ☆25Updated 3 years ago
• embedded-explorer / Open-Source-RTL-Design
  This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
  ☆36Updated 3 years ago