This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
☆44Jun 6, 2021Updated 5 years ago
Alternatives and similar repositories for Open-Source-RTL-Design
Users that are interested in Open-Source-RTL-Design are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 5 days (30 hours) is all what took me to learn the basics and design a pipelined RV32I core. Check this article to know more !☆14Feb 2, 2022Updated 4 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆25Jan 20, 2021Updated 5 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆18Oct 16, 2021Updated 4 years ago
- Verilog ADC interface for adc128s022 found in De0 Nano☆16Jul 7, 2015Updated 11 years ago
- learning VHDL☆12Jul 1, 2014Updated 12 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- HDMI + GPU-pipeline + FFT☆15Mar 4, 2016Updated 10 years ago
- ☆13Apr 12, 2023Updated 3 years ago
- ☆22May 5, 2022Updated 4 years ago
- 16QAM modulation and demodulation by Verilog☆20Jan 4, 2021Updated 5 years ago
- This repository in a walk through the entire process of PLL IC designing from the tools to the final tapeout.☆20Feb 16, 2022Updated 4 years ago
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆22Sep 30, 2026Updated last week
- My second attempt at a RISC-V CPU with learnings form my previous attempt.☆11Apr 27, 2026Updated 5 months ago
- A project for learning RISC-V architecture purpose☆26Nov 9, 2023Updated 2 years ago
- double_fpu_verilog☆22Jul 17, 2014Updated 12 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Project 2.2 Frequency counter☆12May 30, 2025Updated last year
- ☆24Oct 5, 2026Updated last week
- RTL implementation of a ray-tracing GPU☆17Dec 18, 2012Updated 13 years ago
- This is the client side library to access JTAG Server distributed with Quartus (jtagd/jtagserver.exe). The protocol is known as Advanced …☆20Aug 18, 2025Updated last year
- A set of rules and recommendations for analog and digital circuit designers.☆31Nov 4, 2024Updated last year
- ESP8266 powered Xilinx Virtual Cable - Xilinx WiFi JTAG!☆33Aug 25, 2021Updated 5 years ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- ☆16Aug 15, 2021Updated 5 years ago
- The best rtl_uart in github! This is a UART design based on AXI Stream/Ready Vallid protocol. Support parameterized data bit width, clock…☆12May 8, 2025Updated last year
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆16Dec 16, 2021Updated 4 years ago
- Zero to ASIC group submission for MPW2☆13Mar 26, 2025Updated last year
- DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep lea…☆22Sep 11, 2026Updated last month
- This repo is "NTHU Parallel Programing" course project.☆10Dec 5, 2017Updated 8 years ago
- A Cadence Allegro PCB schematics parser and verification tool. Together with IBERTpy can configure, run, and compile Vivado IBERT eye dia…☆13Apr 17, 2021Updated 5 years ago
- A tool for those who want to use Vivado's batch mode more easily☆17Dec 16, 2019Updated 6 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- A deep learning based bioinformatics project on epigenetics in Type 2 Diabetes.☆17Mar 25, 2023Updated 3 years ago
- Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher☆17Feb 27, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- Quad cluster of RISC-V cores with peripherals and local memory☆24Feb 3, 2022Updated 4 years ago
- Not All Patches Are Equal: Hierarchical Dataset Condensation for Single Image Super-Resolution☆10May 7, 2024Updated 2 years ago
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆126Jul 31, 2021Updated 5 years ago
- UEFI app to load ELF and Raw binary☆30May 5, 2015Updated 11 years ago
- A copy of the DirectX Headers from MinGW-64.☆14Sep 7, 2023Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago