embedded-explorer / Open-Source-RTL-DesignLinks
This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
☆41Updated 4 years ago
Alternatives and similar repositories for Open-Source-RTL-Design
Users that are interested in Open-Source-RTL-Design are comparing it to the libraries listed below
Sorting:
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆69Updated 11 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- RISCV model for Verilator/FPGA targets☆53Updated 6 years ago
- pulp_soc is the core building component of PULP based SoCs☆82Updated 10 months ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆81Updated last month
- PCI Express controller model☆71Updated 3 years ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆127Updated 6 months ago
- RISC-V Nox core☆71Updated 6 months ago
- ☆74Updated 5 years ago
- DDR4 Simulation Project in System Verilog☆44Updated 11 years ago
- ☆40Updated 2 years ago
- Basic RISC-V Test SoC☆170Updated 6 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆107Updated 4 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆26Updated 7 years ago
- Platform Level Interrupt Controller☆44Updated last year
- A simple DDR3 memory controller☆61Updated 3 years ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Updated 2 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆48Updated 4 years ago
- RISC-V Verification Interface☆138Updated last week
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆79Updated 3 years ago
- Archives of SystemC from The Ground Up Book Exercises☆33Updated 3 years ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆44Updated 3 years ago
- 64-bit multicore Linux-capable RISC-V processor☆105Updated 9 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆89Updated last year
- Demo SoC for SiliconCompiler.☆62Updated last week
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.☆101Updated 7 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆51Updated 4 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 6 years ago